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SN74LS165N Datasheet(PDF) 6 Page - Motorola, Inc |
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SN74LS165N Datasheet(HTML) 6 Page - Motorola, Inc |
6 / 6 page ![]() 5-283 FAST AND LS TTL DATA SN54/74LS160A • SN54/74LS161A SN54/74LS162A • SN54/74LS163A Figure 3 The positive TC pulse occurs when the outputs are in the (Q0 • Q1 • Q2 • Q3) state for the LS160 and LS162 and the (Q0 • Q1 • Q2 • Q3) state for the LS161 and LS163. OTHER CONDITIONS: CP = PE = CEP = MR = H 1.3 V tPHL tPLH 1.3 V 1.3 V 1.3 V CET TC AC WAVEFORMS (continued) The positive TC pulse is coincident with the output state (Q0 • Q1 • Q2 • Q3) state for the LS161 and LS163 and (Q0 • Q1 • Q2 • Q3) for the LS161 and LS163. Figure 4 OTHER CONDITIONS: PE = CEP = CET = MR = H 1.3 V 1.3 V 1.3 V 1.3 V 1.3 V tPLH tPHL CP TC The shaded areas indicate when the input is permitted to change for predictable output performance. Figure 5 1.3 V 1.3 V OTHER CONDITIONS: PE = L, MR = H CP 1.3 V 1.3 V 1.3 V ts(H) ts(L) th(H) = 0 th(L) = 0 Q0 • Q1 • Q2 • Q3 P0 • P1 • P2 • P3 OTHER CONDITIONS: PE = H, MR = H 1.3 V 1.3 V 1.3 V 1.3 V 1.3 V 1.3 V 1.3 V 1.3 V 1.3 V 1.3 V 1.3 V ts(H) ts(L) th(H) = 0 th(L) = 0 ts(H) th(H) = 0 ts(L) th(L) = 0 COUNT HOLD HOLD CEP CP CET Q CP SR or PE Q RESPONSE TO PE RESET COUNT OR LOAD Q RESPONSE TO SR PARALLEL LOAD (See Fig. 5) COUNT MODE (See Fig. 7) ts(L) ts(H) th (L) = 0 th(H) = 0 1.3 V 1.3 V Figure 6 COUNT ENABLE TRICKLE INPUT TO TERMINAL COUNT OUTPUT DELAYS CLOCK TO TERMINAL COUNT DELAYS SETUP TIME (ts) AND HOLD TIME (th) FOR PARALLEL DATA INPUTS SETUP TIME (ts) AND HOLD TIME (th) FOR COUNT ENABLE (CEP) AND (CET) AND PARALLEL ENABLE (PE) INPUTS Figure 7 The shaded areas indicate when the input is permitted to change for predictable output performance. 1.3 V |
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