AT90S/LS4434 and AT90S/LS8535

4

Figure 1. Oscillator Connections

Figure 2. External Clock Drive Configuration

Architectural Overview

The fast-access register file concept contains 32 x 8-bit

general purpose working registers with a single clock cycle

access time. This means that during one single clock cycle,

one Arithmetic Logic Unit (ALU) operation is executed. Two

operands are output from the register file, the operation is

executed, and the result is stored back in the register file -

in one clock cycle.

Six of the 32 registers can be used as three 16-bits indirect

address register pointers for Data Space addressing -

enabling efficient address calculations. One of the three

address pointers is also used as the address pointer for the

constant table look up function. These added function reg-

isters are the 16-bits X-register, Y-register and Z-register.

Figure 3. The AT90S4434/8535

2K/4K X 16

Program

Memory

Instruction

Register

Instruction

Decoder

Program

Counter

Control Lines

32 x 8

General

Purpose

Registrers

ALU

Status

and Control

Interrupt

Unit

SPI

Unit

8-bit

Timer/Counter

Watchdog

Timer

Analog to Digital

Converter

Analog

Comparator

32

I/O Lines

256/512 x 8

EEPROM

Data Bus 8-bit

AVR AT90S4434/8535 Architecture

Serial

UART

16-bit

Timer/Counter

with PWM

8-bit

Timer/Counter

with PWM

256/512 x 8

Data

SRAM