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AD9432BSQZ-80 Datasheet(PDF) 12 Page - Analog Devices |
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AD9432BSQZ-80 Datasheet(HTML) 12 Page - Analog Devices |
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12 / 20 page  REV. E AD9432 –12– EVALUATION BOARD The AD9432 evaluation board offers an easy way to test the AD9432. It requires an analog signal, encode clock, and power supplies as inputs. The clock is buffered on the board to provide the clocks for an on-board DAC and latches. The digital outputs and output clock are available at a standard 37-pin connector P7. Power Connector Power is supplied to the board via two detachable 4-pin power strips P30, P40. P40 P1 VCC2 5 V/165 mA DAC Supply P2 GND P3 VCC 5 V/200 mA ADC Analog Supply P4 GND P30 P5 No Connect P6 No Connect P7 VD 3.3 V /105 mA Latch, ADC Digital Output Supply P8 GND Analog Inputs The evaluation board accepts a 2 V p-p analog input signal at SMB connector P2. This single-ended signal is ac-coupled by capacitor C11 and drives a wideband RF transformer T1 (Mini- Circuits ADT1-1WT) that converts the single-ended signal to a differential signal. (The AD9432 should be driven differentially to provide optimum performance.) The evaluation board is shipped with termination resistors R4, R5, which provide the effective 50 Ω termination impedance; input termination resistor R10 is optional. Note: The second harmonic distortion that some RF transformers tend to introduce at high frequencies can be reduced by coupling two transformers in series as shown in Figure 13. (Improvements on the order of 3 dB–4 dB can be realized.) IN TO AIN+ R1 25 R2 25 C1 0.1 F TO AIN– T2 T1 C2 0.1 F Figure 13. Improving Second Harmonic Distortion Performance CH2 CH1 CH3 500mV 2.00V 500mV M 5.00ns CH1 3.00V STOP: TEK 5.00GS/s [T] 14 ACQS C1 MAX 3.4V C1 MIN 2.5mV C1 FREQ 49.995MHz LOW SIGNAL AMPLITUDE T 2 Figure 14. Analog Input Levels The full-scale analog inputs to the ADC should be two 1 V p-p signals 180 degrees out of phase with each other, as shown in Figure 14. The analog inputs are dc biased by two on-chip resistor dividers that set the common-mode voltage to approxi- mately 0.6 × VCC (0.6 × 5 = 3 V). AIN+ and AIN– each vary between 2.5 V and 3.5 V as shown in the two upper traces in Fig- ure 14. The lower trace is the input at SMB P2 (on a 2 V/div scale). Encode The encode input to the board is at SMB connector P3. The (>1 V p-p) input is ac-coupled and drives two high-speed differ- ential line receivers (MC10EL16). These receivers provide subnanosecond rise times at their outputs—a requirement for the ADC clock inputs for optimum performance. The EL16 outputs are PECL levels and must be ac-coupled to meet the common-mode dc levels required at the AD9432 encode inputs. A PECL/TTL translator (MC100ELT23), provides the clocks required at the output latches, DAC, and 37-pin connector. Note: Jitter performance on the clock source is critical at this performance level; a stable, crystal-controlled signal generator is used to generate all of the ADC performance plots. Figure 15 shows the Encode+ clock at the ADC. The 3 V latch clock generated on the card is also shown in the plot. [T] 86 ACQS STOP: TEK 5.00GS/s T 2 CH2 CH1 1.00V 1.00V M 5.00ns CH1 1.20V C1 MAX 2.33V C1 MIN 810mV C1 FREQ 106.3167MHz LOW SIGNAL AMPLITUDE Figure 15. Encode+ Clock and Latch Clock |
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