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LMH0387SL Datasheet(PDF) 14 Page - Texas Instruments

Part # LMH0387SL
Description  LMH0387 3 Gbps HD/SD SDI Configurable I/O Adaptive Cable Equalizer / Cable Driver
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
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LMH0387SL Datasheet(HTML) 14 Page - Texas Instruments

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50
100 150 200 250 300 350 400
BELDEN 1694A CABLE LENGTH (m)
0
5
10
15
20
25
30
LMH0387
SNLS315G – APRIL 2010 – REVISED APRIL 2013
www.ti.com
Figure 5. CLI vs. Belden 1694A Cable Length
OUTPUT MODE (CABLE DRIVER) DESCRIPTION
INPUT INTERFACING
The LMH0387 cable driver accepts differential input signals which can be DC or AC coupled.
OUTPUT INTERFACING
The LMH0387 cable driver uses 75
Ω internally terminated current mode outputs. The output level is 800 mVP-P
with an RREF resistor of 715Ω. The RREF resistor is connected between the RREF pin and VCC, and should be
placed as close as possible to the RREF pin.
The output should be AC coupled as shown in the Typical Application Circuit diagram. The TERMTX output must
be properly terminated with a 4.7 µF capacitor followed by a 75
Ω resistor to ground as shown.
OUTPUT SLEW RATE CONTROL
The LMH0387 cable driver output rise and fall times are selectable for either SMPTE 259M or SMPTE 424M /
292M compliance via the SD/HD pin. For slower rise and fall times, or SMPTE 259M compliance, SD/HD is set
high. For faster rise and fall times, or SMPTE 424M and SMPTE 292M compliance, SD/HD is set low. SD/HD
has an internal pulldown.
OUTPUT ENABLE
The LMH0387 cable driver can be enabled or disabled with the TX_EN pin. When set low, the cable driver is
powered off. TX_EN has an internal pullup to enable the cable driver by default. When using the LMH0387 in the
input mode (as an equalizer), the cable driver must be disabled by setting the TX_EN pin low.
APPLICATION INFORMATION
PCB LAYOUT RECOMMENDATIONS
For information on layout and soldering of the laminate TLGA package, pease refer to the following application
note: AN-1125 (SNAA002), “Laminate CSP/FBGA.”
For a CSP package, it is a general requirement not to have any metal (traces or vias) on the top layer in
the area directly underneath the device, other than the footprint. This is intended to provide a flat planar
surface for the package.
14
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Copyright © 2010–2013, Texas Instruments Incorporated
Product Folder Links: LMH0387


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