LMH0387

SNLS315G – APRIL 2010 – REVISED APRIL 2013

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In auto sleep mode, the time to power down the equalizer when the input signal is removed is less than 200 µs

and should not have any impact on the system timing requirements. The equalizer will wake up automatically

once an input signal is detected, and the delay between signal detection and full functionality of the equalizer is

negligible. The overall system will be limited only by the settling time constant of the equalizer adaptation loop.

INPUT MODE (EQUALIZER) SPI REGISTER ACCESS

SPI register access is required for correct input mode (equalizer) operation. The SPI registers provide access to

all of the equalizer features along with a cable length indicator, programmable output common mode voltage and

swing, and launch amplitude optimization. There are four supported 8-bit registers in the device (see Table 1).

Note: The SPI_EN pin must always be pulled high while using the LMH0387 in the input mode (equalizer), and

may optionally be pulled high while using the LMH0387 in the output mode (cable driver) as well.

SPI Write

The SPI write is shown in Figure 2. The MOSI payload consists of a “0” (write command), seven address bits,

and eight data bits. The SS signal is driven low, and the 16 bits are sent to the LMH0387's MOSI input. Data is

latched on the rising edge of SCK. The MISO output is normally tri-stated during this operation. After the SPI

write, SS must return high.

SPI Read

The SPI read is shown in Figure 3. The MOSI payload consists of a “1” (read command) and seven address bits.

The SS signal is driven low, and the eight bits are sent to the LMH0387's MOSI input. The addressed location is

clock. After the SPI read, SS must return high.

GENERAL CONTROL (REGISTER 00h)

SPI Register 00h, General Control, provides access to many basic features of the equalizer, including the carrier

detect status and the mute, sleep mode, and extended 3G reach mode controls.

Carrier Detect

This bit shows the status of the carrier detect for the BNC_IO pin.

Mute

The mute control can be used to manually mute or enable SDO and SDO. Setting this bit to “1” will mute the

equalizer outputs by forcing them to logic zero. Setting the mute bit to “0” will force the equalizer outputs to be

active.

Sleep Mode

The sleep mode is used to automatically or selectively power down the equalizer for power savings when it is not

needed. The auto sleep mode allows the equalizer to power down when no input signal is detected, and is

activated by default or by writing “01” to bits [4:3] of SPI register 00h. If the auto sleep mode is active, the

equalizer goes into a deep power save mode when no input signal is detected on the BNC_IO pin. The device

powers on again once an input signal is detected. The sleep functionality can be turned off completely (equalizer

will never sleep) by writing “00” to bits [4:3] of SPI register 00h. Additionally, the equalizer can be forced to power

down regardless of whether there is an input signal or not by writing “10” to bits [4:3] of SPI register 00h. The

sleep mode has precedence over the mute mode.

Extended 3G Reach Mode

The LMH0387 equalizer provides a mode to extend the 3G cable reach in systems which have margin in the jitter

budget. This allows for additional cable reach at 2.97 Gbps at the expense of slightly higher output jitter. The

extended 3G reach mode provides 10m of additional Belden 1694A cable reach, with an increase of output jitter

at this longer cable length of 0.05 to 0.1 UI. (Note: In Extended 3G Reach Mode, the maximum equalizable cable

lengths for HD and SD data rates will be limited to less than what can be achieved in normal mode).

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