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PIC18F2680ISOSQTP Datasheet(PDF) 389 Page - Microchip Technology |
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PIC18F2680ISOSQTP Datasheet(HTML) 389 Page - Microchip Technology |
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389 / 482 page ![]() © 2007 Microchip Technology Inc. Preliminary DS39625C-page 387 PIC18F2585/2680/4585/4680 MOVLW Move Literal to W Syntax: MOVLW k Operands: 0 ≤ k ≤ 255 Operation: k → W Status Affected: None Encoding: 0000 1110 kkkk kkkk Description: The eight-bit literal ‘k’ is loaded into W. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read literal ‘k’ Process Data Write to W Example: MOVLW 5Ah After Instruction W= 5Ah MOVWF Move W to f Syntax: MOVWF f {,a} Operands: 0 ≤ f ≤ 255 a ∈ [0,1] Operation: (W) → f Status Affected: None Encoding: 0110 111a ffff ffff Description: Move data from W to register ‘f’. Location ‘f’ can be anywhere in the 256-byte bank. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default). If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Section 25.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data Write register ‘f’ Example: MOVWF REG, 0 Before Instruction W= 4Fh REG = FFh After Instruction W= 4Fh REG = 4Fh |
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