PIC18F2680ISOSQTP datasheet(377/482 Pages) MICROCHIP

377 / 482 page

Preliminary

DS39625C-page 375

PIC18F2585/2680/4585/4680

BTG

Bit Toggle f

Syntax:

BTG f, b {,a}

Operands:

≤ f ≤ 255

≤ b < 7

∈ [0,1]

Operation:

(f<b>)

→ f<b>

Status Affected:

None

Encoding:

0111

bbba

ffff

Description:

Bit ‘b’ in data memory location ‘f’ is

inverted.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset addressing

mode whenever f

≤ 95 (5Fh). See

Section 25.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words:

Cycles:

Q Cycle Activity:

Decode

Read

Process

Data

Write

Example:

BTG

PORTC,

4, 0

Before Instruction:

PORTC

0111 0101

[75h]

After Instruction:

PORTC

0110 0101

[65h]

BOV

Branch if Overflow

Syntax:

BOV

Operands:

-128

≤ n ≤ 127

Operation:

if Overflow bit is ‘1’

(PC) + 2 + 2n

→ PC

Status Affected:

None

Encoding:

1110

0100

nnnn

Description:

If the Overflow bit is ‘1’, then the

program will branch.

The 2’s complement number ‘2n’ is

added to the PC. Since the PC will

have incremented to fetch the next

instruction, the new address will be

PC + 2 + 2n. This instruction is then a

two-cycle instruction.

Words:

Cycles:

1(2)

Q Cycle Activity:

If Jump:

Decode

Read literal

‘n’

Process

Data

Write to PC

operation

If No Jump:

Decode

Read literal

‘n’

Process

Data

operation

Example:

HERE

BOV

Jump

Before Instruction

address (HERE)

After Instruction

If Overflow

address (Jump)

If Overflow

address (HERE + 2)

PIC18F2680ISOSQTP Datasheet(PDF) 377 Page - Microchip Technology

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