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A8351601L-40 Datasheet(PDF) 13 Page - AMIC Technology |
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A8351601L-40 Datasheet(HTML) 13 Page - AMIC Technology |
13 / 44 page A8351601 Series (July, 2002, Version 1.0) 12 AMIC Technology, Inc. PWM1: Pulse Width Modulation 1 Register. Not Bit Addressable. 7 6 5 4 3 2 1 0 - PWM1.6 PWM1.5 PWM1.4 PWM1.3 PWM1.2 PWM1.1 PWM1.0 Register Description: PWM1.7 PWM4 output control. Set/Clear by specify 75% duty/67% duty. PWM1.6 PWM1 frequency control bit. Set/Cleared by specify half/normal PWM1 frequency. PWM1.5 PWM1 cycle control bit. PWM1.4 PWM1 cycle control bit. PWM1.3 PWM1 cycle control bit. PWM1.2 PWM1 cycle positive edge width control bit. PWM1.1 PWM1 cycle positive edge width control bit. PWM1.0 PWM1 cycle positive edge width control bit. Note: PWM1 PWM3 PWM4 Delay 4~11 CLK T3 3072 T3(PWM1.7:1)/2048 T3(PWM1.7:0) 1024 T3 Xtal frequency = 14.7456MHz Bit<5:3> 0 1 2 3 4 5 6 7 T1 1.017us 1.695us 2.373us 3.051us 3.729us 4.407us 5.085us 5.763us Bit<2:0> 0 1 2 3 4 5 6 7 T2 542.4ns 67.8ns 135.6ns 203.4ns 271.2ns 339ns 406.8ns 474.6ns T2 T1 |
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