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A420616 Datasheet(PDF) 3 Page - AMIC Technology |
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A420616 Datasheet(HTML) 3 Page - AMIC Technology |
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3 / 25 page  A420616 Series PRELIMINARY (June, 2002, Version 0.2) 2 AMIC Technology, Inc. Selection Guide Symbol Description -45 -50 Unit tRAC Maximum RAS Access Time 45 50 ns tAA Maximum Column Address Access Time 20 22 ns tCAC Maximum CAS Access Time 12 13 ns tOEA Maximum Output Enable ( OE ) Access Time 12 13 ns tRC Minimum Read or Write Cycle Time 76 84 ns tPC Minimum EDO Cycle Time 18 20 ns Functional Description The A420616 reads and writes data by multiplexing an 20- bit address into a 10-bit row and 10-bit column address. RAS and CAS are used to strobe the row address and the column address, respectively. The A420616 has two CAS inputs: LCAS controls I/O0- I/O7, and UCAS controls I/O8 - I/O15, UCAS and LCAS function in an identical manner to CAS in that either will generate an internal CAS signal. The CAS function and timing are determined by the first CAS ( UCAS or LCAS ) to transition low and by the last to transition high. Byte Read and Byte Write are controlled by using LCAS and UCAS separately. A Read cycle is performed by holding the WE signal high during RAS / CAS operation. A Write cycle is executed by holding the WE signal low during RAS / CAS operation; the input data is latched by the falling edge of WE or CAS , whichever occurs later. The data inputs and outputs are routed through 16 common I/O pins, with RAS , CAS , WE and OE controlling the in direction. EDO Page Mode operation all 1024(1K) columns within a selected row to be randomly accessed at a high data rate. A EDO Page Mode cycle is initiated with a row address latched by RAS followed by a column address latched by CAS . While holding RAS low, CAS can be toggled to strobe changing column addresses, thus achieving shorter cycle times. The A420616 offers an accelerated Fast Page Mode cycle through a feature called Extended Data Out, which keeps the output drivers on during the CAS precharge time (tcp). Since data can be output after CAS goes high, the user is not required to wait for valid data to appear before starting the next access cycle. Data-out will remain valid as long as RAS and OE are low, and WE is high; this is the only characteristic which differentiates Extended Data Out operation from a standard Read or Fast Page Read. A memory cycle is terminated by returning both RAS and CAS high. Memory cell data will retain its correct state by maintaining power and accessing all 1024(1K) combinations of the 10-bit row addresses, regardless of sequence, at least once every 16ms through any RAS cycle (Read, Write) or RAS Refresh cycle ( RAS -only, CBR, or Hidden). The CBR Refresh cycle automatically controls the row addresses by invoking the refresh counter and controller. Power-On The initial application of the VCC supply requires a 200 µs wait followed by a minimum of any eight initialization cycles containing a RAS clock. During Power-On, the VCC current is dependent on the input levels of RAS and CAS . It is recommended that RAS and CAS track with VCC or be held at a valid VIH during Power-On to avoid current surges. |
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