Oplink Communications, Inc.

Application Notes

Interface Circuit

DIFFERENTIAL

DIRECT-COUPLED PECL

STX-48

7 / 18

50 ohm line

50 ohm line

50 ohm line

50 ohm line

0.01

VCC - 2 V

5 / 20

DATA+ / CLK+

DATA- / CLK-

6 / 19

STX-48

7 / 18

0.01

0.022

5 / 20

DATA+/

CLK+

6 / 19

0.022

DATA-/

CLK-

DIFFERENTIAL

AC-COUPLED

Control

Circuit

Bias

Circuit

200Ω

10Ω

PD

LD

3KΩ

3KΩ

FM+

BM+

VCC

VCC

VEE

VEE

FM -

BM -

3KΩ

3KΩ

T

DC

DATA

CLOCK

Monitor Circuit

Timing Diagram (Clocked Operation)

STX48 Series

R04.2008.04.30

3

When the DATA+ input is at logic HIGH and DATA- input is

at logic LOW, the LD is ON; and vice versa. The transmitter is

normally enabled (i.e. when the TX DISABLE control input is

not connected). When theTX DISABLE input voltage is higher

than V

power) independent of the input data.

The transmitter incorporates an Average Power Control (APC)

loop to stabilize the transmitter average optical output power

against temperature variation. The APC loop always acts

to keep the transmitter average optical output power at a

constant value (when the transmitter is enabled). Therefore,

when the input data is all continuous“zeroes”or all continuous

“ones”, the transmitter optical output power is a constant level

equal to the nominal average optical output power (not at the

“OFF” level or at the “ON” level).

When the MODE SELECTOR input is left unconnected or at

logic “LOW” (V

operation mode. In this mode, the input clock resynchronizes

the incoming data to reduce timing jitter.The timing between

the DATA and CLOCK inputs is as shown below. When the

MODE SELECTOR input at logic “HIGH” (V

the transmitter is in non-clocked operation mode. In this

mode, the CLOCK inputs are not used and hence need not

be provided.

The transmitter has internal 50 ohm termination to V

for DATA inputs & V

CLOCK interface can be either direct PECL/ECL coupling or via

AC coupling as shown below. The use of differential signals is

strongly recommended. In cases where only single-ended signal

is available, the unused DATA input pin should be biased to V

CC

- 1.29 V for direct PECL/ ECL coupling or bypassed to AC Ground

for AC coupling. Similarly, the unused CLOCK input pin should

be bypassed with a 0.01 μF capacitor to V