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AM29LV800B Datasheet(PDF) 15 Page - Advanced Micro Devices |
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AM29LV800B Datasheet(HTML) 15 Page - Advanced Micro Devices |
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15 / 42 page  Am29LV800B 15 P R E L I M I NARY mand. The device then enters the autoselect mode, and the system may read at any address any number of times, without initiating another command sequence. A read cycle at address XX00h retrieves the manufac- turer code. A read cycle at address XX01h in word mode (or 02h in byte mode) returns the device code. A read cycle containing a sector address (SA) and the address 02h in word mode (or 04h in byte mode) re- turns 01h if that sector is protected, or 00h if it is unpro- tected. Refer to Tables 2 and 3 for valid sector addresses. The system must write the reset command to exit the autoselect mode and return to reading array data. Word/Byte Program Command Sequence The system may program the device by word or byte, depending on the state of the BYTE# pin. Program- ming is a four-bus-cycle operation. The program com- mand sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further controls or tim- ings. The device automatically provides internally gen- erated program pulses and verifies the programmed cell margin. Table 5 shows the address and data re- quirements for the byte program command sequence. When the Embedded Program algorithm is complete, the device then returns to reading array data and ad- dresses are no longer latched. The system can deter- mine the status of the program operation by using DQ7, DQ6, or RY/BY#. See “Write Operation Status” for information on these status bits. Any commands written to the device during the Em- bedded Program Algorithm are ignored. Note that a hardware reset immediately terminates the program- ming operation. The program command sequence should be reinitiated once the device has reset to read- ing array data, to ensure data integrity. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from a “0” back to a “1”. Attempting to do so may halt the operation and set DQ5 to “1”, or cause the Data# Polling algorithm to indicate the operation was suc- cessful. However, a succeeding read will show that the data is still “0”. Only erase operations can convert a “0” to a “1”. Unlock Bypass Command Sequence The unlock bypass feature allows the system to pro- gram bytes or words to the device faster than using the standard program command sequence. The unlock by- pass command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the unlock bypass command, 20h. The de- vice then enters the unlock bypass mode. A two-cycle unlock bypass program command sequence is all that is required to program in this mode. The first cycle in this sequence contains the unlock bypass program command, A0h; the second cycle contains the program address and data. Additional data is programmed in the same manner. This mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total program- ming time. Table 5 shows the requirements for the com- mand sequence. During the unlock bypass mode, only the Unlock By- pass Program and Unlock Bypass Reset commands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset com- mand sequence. The first cycle must contain the data 90h; the second cycle the data 00h. Addresses are don’t care for both cycles. The device then returns to reading array data. Figure 3 illustrates the algorithm for the program oper- ation. See the Erase/Program Operations table in “AC Characteristics” for parameters, and to Figure 17 for timing diagrams. |
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