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PXAG49KBBD Datasheet(PDF) 8 Page - NXP Semiconductors |
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PXAG49KBBD Datasheet(HTML) 8 Page - NXP Semiconductors |
8 / 42 page Philips Semiconductors Preliminary data XA-G49 XA 16-bit microcontroller family 64K Flash/2K RAM, watchdog, 2 UARTs 2001 Jun 27 8 NAME RESET VALUE BIT FUNCTIONS AND ADDRESSES SFR ADDRESS DESCRIPTION NAME RESET VALUE LSB MSB SFR ADDRESS DESCRIPTION 357 356 355 354 353 352 351 350 SWR* Software Interrupt Request 42A — SWR7 SWR6 SWR5 SWR4 SWR3 SWR2 SWR1 00 2C7 2C6 2C5 2C4 2C3 2C2 2C1 2C0 T2CON* Timer 2 control register 418 TF2 EXF2 RCLK0 TCLK0 EXEN2 TR2 C/T2 CP/RL2 00 2CF 2CE 2CD 2CC 2CB 2CA 2C9 2C8 T2MOD* Timer 2 mode control 419 — — RCLK1 TCLK1 — — T2OE DCEN 00 TH2 Timer 2 high byte 459 00 TL2 Timer 2 low byte 458 00 T2CAPH Timer 2 capture register, high byte 45B 00 T2CAPL Timer 2 capture register, low byte 45A 00 287 286 285 284 283 282 281 280 TCON* Timer 0 and 1 control register 410 TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 00 TH0 Timer 0 high byte 451 00 TH1 Timer 1 high byte 453 00 TL0 Timer 0 low byte 450 00 TL1 Timer 1 low byte 452 00 TMOD Timer 0 and 1 mode control 45C GATE C/T M1 M0 GATE C/T M1 M0 00 28F 28E 28D 28C 28B 28A 289 288 TSTAT* Timer 0 and 1 extended status 411 — — — — — T1OE — T0OE 00 2FF 2FE 2FD 2FC 2FB 2FA 2F9 2F8 WDCON* Watchdog control register 41F PRE2 PRE1 PRE0 — — WDRUN WDTOF — Note 6 WDL Watchdog timer reload 45F 00 WFEED1 Watchdog feed 1 45D x WFEED2 Watchdog feed 2 45E x NOTES: * SFRs are bit addressable. 1. At reset, the BCR register is loaded with the binary value 0000 0a11, where “a” is the value on the BUSW pin. This defaults the address bus size to 20 bits since the XA-G49 has only 20 address lines. 2. SFR is loaded from the reset vector. 3. All bits except F1, F0, and P are loaded from the reset vector. Those bits are all 0. 4. Unimplemented bits in SFRs are X (unknown) at all times. Ones should not be written to these bits since they may be used for other purposes in future XA derivatives. The reset value shown for these bits is 0. 5. Port configurations default to quasi-bidirectional when the XA begins execution from internal code memory after reset, based on the condition found on the EA pin. Thus all PnCFGA registers will contain FF and PnCFGB registers will contain 00. When the XA begins execution using external code memory, the default configuration for pins that are associated with the external bus will be push-pull. The PnCFGA and PnCFGB register contents will reflect this difference. 6. The WDCON reset value is E6 for a Watchdog reset, E4 for all other reset causes. 7. The XA-G49 implements an 8-bit SFR bus, as stated in Chapter 8 of the XA User Guide. All SFR accesses must be 8-bit operations. Attempts to write 16 bits to an SFR will actually write only the lower 8 bits. Sixteen bit SFR reads will return undefined data in the upper byte. 8. The AUXR reset value is typically 00h. If the Boot Loader is activated at reset because the Flash status byte is non-zero or because the Boot Vector has been forced (by PSEN = 0, ALE = 1, EA = 1 at reset), the AUXR reset value will be 1x00 0000b. Bit 6 will be a 1 if the on-chip VPP generator is running and ready, otherwise it will be a 0. |
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