Philips Semiconductors

Preliminary data

XA-G49

XA 16-bit microcontroller family

64K Flash/2K RAM, watchdog, 2 UARTs

2001 Jun 27

33

AC ELECTRICAL CHARACTERISTICS (5 V)

SYMBOL

FIGURE

PARAMETER

VARIABLE CLOCK

UNIT

SYMBOL

FIGURE

PARAMETER

MIN

MAX

UNIT

External Clock

Oscillator frequency

0

30

MHz

26

Clock period and CPU timing cycle

ns

26

Clock high time

ns

26

Clock low time

ns

26

Clock rise time

5

ns

26

Clock fall time

5

ns

Address Cycle

25

Delay from clock rising edge to ALE rising edge

5

46

ns

20

ALE pulse width (programmable)

ns

20

Address valid to ALE de-asserted (set-up)

ns

20

Address hold after ALE de-asserted

ns

Code Read Cycle

20

PSEN pulse width

ns

20

ALE de-asserted to PSEN asserted

ns

20

Address valid to instruction valid, ALE cycle (access time)

ns

21

Address valid to instruction valid, non-ALE cycle (access time)

ns

20

PSEN asserted to instruction valid (enable time)

ns

20

Instruction hold after PSEN de-asserted

0

ns

20

Bus 3-State after PSEN de-asserted (disable time)

ns

20

Hold time of unlatched part of address after instruction latched

0

ns

Data Read Cycle

22

RD pulse width

ns

22

ALE de-asserted to RD asserted

ns

22

Address valid to data input valid, ALE cycle (access time)

ns

23

Address valid to data input valid, non-ALE cycle (access time)

ns

22

RD low to valid data in, enable time

ns

22

Data hold time after RD de-asserted

0

ns

22

Bus 3-State after RD de-asserted (disable time)

ns

22

Hold time of unlatched part of address after data latched

0

ns

Data Write Cycle

24

WR pulse width

ns

24

ALE falling edge to WR asserted

ns

24

Data valid before WR asserted (data setup time)

ns

24

Data hold time after WR de-asserted (Note 6)

ns

24

Address valid to WR asserted (address setup time) (Note 5)

ns

24

Hold time of unlatched part of address after WR is de-asserted

ns

Wait Input

25

WAIT stable after bus strobe (RD, WR, or PSEN) asserted

ns

25

WAIT hold after bus strobe (RD, WR, or PSEN) assertion

ns

NOTES:

1. Load capacitance for all outputs = 80pF.

2. Variables V1 through V13 reflect programmable bus timing, which is programmed via the Bus Timing registers (BTRH and BTRL).

Refer to the

XA User Guide for details of the bus timing settings.

V1)

This variable represents the programmed width of the ALE pulse as determined by the ALEW bit in the BTRL register.

V1 = 0.5 if the ALEW bit = 0, and 1.5 if the ALEW bit = 1.