Philips Semiconductors

Preliminary data

XA-G49

XA 16-bit microcontroller family

64K Flash/2K RAM, watchdog, 2 UARTs

2001 Jun 27

29

BIT

SYMBOL

FUNCTION

SnCON.5

SM2

Enables the multiprocessor communication feature in Modes 2 and 3. In Mode 2 or 3, if SM2 is set to 1, then RI

will not be activated if the received 9th data bit (RB8) is 0. In Mode 1, if SM2=1 then RI will not be activated if a

valid stop bit was not received. In Mode 0, SM2 should be 0.

SnCON.4

REN

Enables serial reception. Set by software to enable reception. Clear by software to disable reception.

SnCON.3

TB8

The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as desired. The TB8 bit is not

double buffered. See text for details.

SnCON.2

RB8

In Modes 2 and 3, is the 9th data bit that was received. In Mode 1, if SM2=0, RB8 is the stop bit that was

received. In Mode 0, RB8 is not used.

SnCON.1

TI

Transmit interrupt flag. Set when another byte may be written to the UART transmitter. See text for details.

Must be cleared by software.

SnCON.0

RI

Receive interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or at the end of the stop bit time

in the other modes (except see SM2). Must be cleared by software.

Where SM0, SM1 specify the serial port mode, as follows:

SM0

SM1

Mode

Description

Baud Rate

0

0

0

shift register

0

1

1

8-bit UART

variable

1

0

2

9-bit UART

1

1

3

9-bit UART

variable

SU00597C

RI

TI

RB8

TB8

REN

SM2

SM1

SM0

SnCON

Address:

S0CON 420

S1CON 424

Bit Addressable

Reset Value: 00H

LSB

MSB

Figure 16. Serial Port Control (SnCON) Register

D0

D1

D2

D3

D4

D5

D6

D7

D8

STOP

BIT

DATA BYTE

ONLY IN

MODE 2, 3

START

BIT

SU00598

—

—

—

—

FEn

BRn

OEn

STINTn

SnSTAT

if 0, sets FE

Figure 17. UART Framing Error Detection

SM0_n

SM1_n

SM2_n

REN_n

TB8_n

RB8_n

TI_n

RI_n

SnCON

D0

D1

D2

D3

D4

D5

D6

D7

D8

1

1

1

0

COMPARATOR

11

X

RECEIVED ADDRESS D0 TO D7

PROGRAMMED ADDRESS

IN UART MODE 2 OR MODE 3 AND SM2 = 1:

INTERRUPT IF REN=1, RB8=1 AND “RECEIVED ADDRESS” = “PROGRAMMED ADDRESS”

– WHEN OWN ADDRESS RECEIVED, CLEAR SM2 TO RECEIVE DATA BYTES

– WHEN ALL DATA BYTES HAVE BEEN RECEIVED: SET SM2 TO WAIT FOR NEXT ADDRESS.

SU00613

Figure 18. UART Multiprocessor Communication, Automatic Address Recognition