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PXAG49KBBD Datasheet(PDF) 27 Page - NXP Semiconductors |
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PXAG49KBBD Datasheet(HTML) 27 Page - NXP Semiconductors |
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27 / 42 page  Philips Semiconductors Preliminary data XA-G49 XA 16-bit microcontroller family 64K Flash/2K RAM, watchdog, 2 UARTs 2001 Jun 27 27 CLOCKING SCHEME/BAUD RATE GENERATION The XA UARTS clock rates are determined by either a fixed division (modes 0 and 2) of the oscillator clock or by the Timer 1 or Timer 2 overflow rate (modes 1 and 3). The clock for the UARTs in XA runs at 16x the Baud rate. If the timers are used as the source for Baud Clock, since maximum speed of timers/Baud Clock is Osc/4, the maximum baud rate is timer overflow divided by 16 i.e. Osc/64. In Mode 0, it is fixed at Osc/16. In Mode 2, however, the fixed rate is Osc/32. 00 Osc/4 Pre-scaler f ll Ti T012 01 Osc/16 for all Timers T0,1,2 controlled by PT1, PT0 10 Osc/64 controlled by PT1, PT0 bits in SCR 11 reserved Baud Rate for UART Mode 0: Baud_Rate = Osc/16 Baud Rate calculation for UART Mode 1 and 3: Baud_Rate = Timer_Rate/16 Timer_Rate = Osc/(N*(Timer_Range– Timer_Reload_Value)) where N = the TCLK prescaler value: 4, 16, or 64. and Timer_Range = 256 for timer 1 in mode 2. 65536 for timer 1 in mode 0 and timer 2 in count up mode. The timer reload value may be calculated as follows: Timer_Reload_Value = Timer_Range–(Osc/(Baud_Rate*N*16)) NOTES: 1. The maximum baud rate for a UART in mode 1 or 3 is Osc/64. 2. The lowest possible baud rate (for a given oscillator frequency and N value) may be found by using a timer reload value of 0. 3. The timer reload value may never be larger than the timer range. 4. If a timer reload value calculation gives a negative or fractional result, the baud rate requested is not possible at the given oscillator frequency and N value. Baud Rate for UART Mode 2: Baud_Rate = Osc/32 Using Timer 2 to Generate Baud Rates Timer T2 is a 16-bit up/down counter in XA. As a baud rate generator, timer 2 is selected as a clock source for either/both UART0 and UART1 transmitters and/or receivers by setting TCLKn and/or RCLKn in T2CON and T2MOD. As the baud rate generator, T2 is incremented as Osc/N where N = 4, 16 or 64 depending on TCLK as programmed in the SCR bits PT1, and PTO. So, if T2 is the source of one UART, the other UART could be clocked by either T1 overflow or fixed clock, and the UARTs could run independently with different baud rates. T2CON bit5 bit4 0x418 RCLK0 TCLK0 T2MOD bit5 bit4 0x419 RCLK1 TCLK1 Prescaler Select for Timer Clock (TCLK) SCR bit3 bit2 0x440 PT1 PT0 STINTn BIT SYMBOL FUNCTION SnSTAT.3 FEn Framing Error flag is set when the receiver fails to see a valid STOP bit at the end of the frame. Cleared by software. SnSTAT.2 BRn Break Detect flag is set if a character is received with all bits (including STOP bit) being logic ‘0’. Thus it gives a “Start of Break Detect” on bit 8 for Mode 1 and bit 9 for Modes 2 and 3. The break detect feature operates independently of the UARTs and provides the START of Break Detect status bit that a user program may poll. Cleared by software. SnSTAT.1 OEn Overrun Error flag is set if a new character is received in the receiver buffer while it is still full (before the software has read the previous character from the buffer), i.e., when bit 8 of a new byte is received while RI in SnCON is still set. Cleared by software. SnSTAT.0 STINTn This flag must be set to enable any of the above status flags to generate a receive interrupt (RIn). The only way it can be cleared is by a software write to this register. SU00607B OEn BRn FEn — — — — SnSTAT Address: S0STAT 421 S1STAT 425 Bit Addressable Reset Value: 00H LSB MSB Figure 15. Serial Port Extended Status (SnSTAT) Register (See also Figure 17 regarding Framing Error flag) |
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