MC74HC240A

http://onsemi.com

2

LOGIC DIAGRAM

DATA

INPUTS

A1

A2

A3

A4

B1

B2

B3

B4

17

15

13

11

8

6

4

218

16

14

12

9

7

5

3

YB4

YB3

YB2

YB1

YA4

YA3

YA2

YA1

INVERTING

OUTPUTS

PIN 10 = GND

OUTPUT

ENABLES

ENABLE A

ENABLE B

1

19

FUNCTION TABLE

Inputs

Outputs

Enable A,

Enable B

A, B

YA, YB

LL

H

LH

L

HX

Z

Z = high impedance

PIN ASSIGNMENT

A3

A2

YB4

A1

ENABLE A

GND

YB1

A4

YB2

YB3

5

4

3

2

1

10

9

8

7

6

14

15

16

17

18

19

20

11

12

13

YA2

B4

YA1

ENABLE B

B1

YA4

B2

YA3

B3

ORDERING INFORMATION

Device

Package

MC74HC240ANG

PDIP−20

(Pb−Free)

18 Units / Box

MC74HC240ADWG

SOIC−20 WIDE

(Pb−Free)

38 Units / Rail

MC74HC240ADWR2G

SOIC−20 WIDE

(Pb−Free)

1000 Tape & Reel

MC74HC240ADTR2G

TSSOP−20*

2500 Tape & Reel

MC74HC240AFG

SOEIAJ−20

(Pb−Free)

40 Units / Rail

MC74HC240AFELG

SOEIAJ−20

(Pb−Free)

2000 Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

*This package is inherently Pb−Free.