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DAC8532IDGKG4 Datasheet(PDF) 14 Page - Texas Instruments |
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DAC8532IDGKG4 Datasheet(HTML) 14 Page - Texas Instruments |
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14 / 23 page  DAC8532 14 SBAS246A www.ti.com DAC8532 to Microwire INTERFACE Figure 7 shows an interface between the DAC8532 and any Microwire compatible device. Serial data is shifted out on the falling edge of the serial clock and is clocked into the DAC8532 on the rising edge of the SK signal. MICROPROCESSOR INTERFACING DAC8532 to 8051 INTERFACE Figure 6 shows a serial interface between the DAC8532 and a typical 8051-type microcontroller. The setup for the inter- face is as follows: TXD of the 8051 drives SCLK of the DAC8532, while RXD drives the serial data line of the device. The SYNC signal is derived from a bit-programmable pin on the port of the 8051. In this case, port line P3.3 is used. When data is to be transmitted to the DAC8532, P3.3 is taken LOW. The 8051 transmits data in 8-bit bytes; thus only eight falling clock edges occur in the transmit cycle. To load data to the DAC, P3.3 is left LOW after the first eight bits are transmitted, then a second and third write cycle is initiated to transmit the remaining data. P3.3 is taken HIGH following the completion of the third write cycle. The 8051 outputs the serial data in a format which presents the LSB first, while the DAC8532 requires its data with the MSB as the first bit received. The 8051 transmit routine must therefore take this into account, and “mirror” the data as needed. The 68HC11 should be configured so that its CPOL bit is 0 and its CPHA bit is 1. This configuration causes data appear- ing on the MOSI output to be valid on the falling edge of SCK. When data is being transmitted to the DAC, the SYNC line is held LOW (PC7). Serial data from the 68HC11 is transmitted in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. (Data is transmitted MSB first.) In order to load data to the DAC8532, PC7 is left LOW after the first eight bits are transferred, then a second and third serial write operation is performed to the DAC. PC7 is taken HIGH at the end of this procedure. DAC8532 to TMS320 DSP INTERFACE Figure 9 shows the connections between the DAC8532 and a TMS320 digital signal processor. By decoding the FSX signal, multiple DAC8532s can be connected to a single serial port of the DSP. FIGURE 6. DAC8532 to 80C51/80L51 Interface. FIGURE 7. DAC8532 to Microwire Interface. FIGURE 8. DAC8532 to 68HC11 Interface. DAC8532 to 68HC11 INTERFACE Figure 8 shows a serial interface between the DAC8532 and the 68HC11 microcontroller. SCK of the 68HC11 drives the SCLK of the DAC8532, while the MOSI output drives the serial data line of the DAC. The SYNC signal is derived from a port line (PC7), similar to the 8051 diagram. FIGURE 9. DAC8532 to TMS320 DSP. DAC8532 TMS320 DSP SYNC D IN SCLK FSX DX CLKX V DD V OUTA V OUTB Output A Output B Reference Input V REF GND 0.1 µF1µF to 10µF Positive Supply 0.1 µF10µF APPLICATIONS CURRENT CONSUMPTION The DAC8532 typically consumes 250uA at VDD = 5V and 225uA at VDD = 3V for each active channel, including refer- ence current consumption. Additional current consumption can occur at the digital inputs if VIH<<VDD. For most efficient power operation, CMOS logic levels are recommended at the digital inputs to the DAC. In power-down mode, typical current consumption is 200nA. A delay time of 10 to 20ms after a power-down command is issued to the DAC is typically sufficient for the power-down current to drop below 10 µA. 80C51/80L51(1) P3.3 TXD RXD DAC8532(1) SYNC SCLK D IN NOTE: (1) Additional pins omitted for clarity. SYNC SCLK D IN MicrowireTM CS SK SO DAC8532(1) NOTE: (1) Additional pins omitted for clarity. Microwire is a registered trademark of National Semiconductor. 68HC11(1) PC7 SCK MOSI SYNC SCLK D IN DAC8532(1) NOTE: (1) Additional pins omitted for clarity. |
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