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DAC8532IDGKG4 Datasheet(PDF) 12 Page - Texas Instruments |
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DAC8532IDGKG4 Datasheet(HTML) 12 Page - Texas Instruments |
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12 / 23 page  DAC8532 12 SBAS246A www.ti.com D17 D16 PD1 PD0 01 1k Ω 1 0 100k Ω 1 1 High Impedance TABLE III. Power-Down Commands. OUTPUT IMPEDANCE POWERDOWN COMMANDS 00 LDB LDA X Buffer Select PD1 PD0 D15 D14 D13 D12 D11 D10 D9D8D7 D6D5D4D3 D2D1 D0 DB11 DB0 FIGURE 5. DAC8532 Data Input Register Format. DB23 DB12 D23 D22 D21 D20 D19 D18 D17 D16 Reserved Reserved Load B Load A Don’t Care Buffer Select PD1 PD0 0 = A, 1 = B 0 0 0 0 X # 0 0 Data WR Buffer # w/Data 0 0 0 0 X # X WR Buffer # w/Power-Down Command 0 0 0 1 X # 0 0 Data WR Buffer # w/Data and Load DAC A 00 0 1 X 0 X WR Buffer A w/Power-Down Command and LOAD DAC A (DAC A Powered Down) 0 0 0 1 X 1 X WR Buffer B w/ Power-Down Command and LOAD DAC A 0 0 1 0 X # 0 0 Data WR Buffer # w/Data and Load DAC B 0 0 1 0 X 0 X WR Buffer A w/Power-Down Command and LOAD DAC B 00 1 0 X 1 X WR Buffer B w/ Power-Down Command and LOAD DAC B (DAC B Powered Down) 0 0 1 1 X # 0 0 Data WR Buffer # w/Data and Load DACs A and B 00 1 1 X 0 X WR Buffer A w/Power-Down Command and Load DACs A and B (DAC A Powered Down) 00 1 1 X 1 X WR Buffer B w/Power-Down Command and Load DACs A and B (DAC B Powered Down) D15 D14 D13-D0 MSB MSB-1 MSB-2...LSB (see Table III) (see Table III) (see Table III) (Always Write 0) TABLE II. Control Matrix. DESCRIPTION (see Table III) (see Table III) (see Table III) (see Table III) SCLK SYNC DIN Invalid Write-Sync Interrupt: SYNC HIGH before 24th Falling Edge Valid Write -Buffer/DAC Update: SYNC HIGH after 24th Falling Edge DB23 DB22 12 12 DB0 DB23 DB22 DB1 DB0 24th Falling Edge 24th Falling Edge FIGURE 4. Interrupt and Valid SYNC Timing. |
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