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APW7158 Datasheet(PDF) 19 Page - Anpec Electronics Coropration

Part # APW7158
Description  Dual Synchronous Buck PWM Controllers
Download  24 Pages
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Manufacturer  ANPEC [Anpec Electronics Coropration]
Direct Link  http://www.anpec.com.tw
Logo ANPEC - Anpec Electronics Coropration

APW7158 Datasheet(HTML) 19 Page - Anpec Electronics Coropration

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Copyright
© ANPEC Electronics Corp.
Rev. A.2 - Aug., 2009
APW7158
www.anpec.com.tw
19
Application Information (Cont.)
increased, and continue to regulate up until the MOSFETs
is damaged. The resistance of the short should include
wiring, PCB traces, contact resistances, and all of the
return paths.
The higher duty cycle will give a higher COMP voltage
level, and it is easy to touch the trip point. The compensa-
tion components also affect the response of COMP
voltage; smaller caps may give a faster response.
The output current has faster rising time during short;
the COMP pin will have a sharp rise. However, if the cur-
rent rises too fast, it may cause a false trip. The output
capacitance and its ESR can affect the rising time of the
current during short.
Short Circuit Protection (Cont.)
Layout Consideration
In high power switching regulator, a correct layout is im-
portant to ensure proper operation of the regulator. In
general, interconnecting impedances should be mini-
mized by using short, wide printed circuit traces.
Signal and power grounds are to be kept separate and
finally combined using ground plane construction or
single point grounding. Figure 10 illustrates the layout,
with bold lines indicating high current paths; these traces
must be short and wide. Components along the bold
lines should be placed lose together. Below is a check-
list for your layout :
The metal plate of the bottom of the packages (SOP-
20) must be soldered to the PCB and connected to the
GND plane on the backside through several thermal vias.
Keep the switching nodes (UGATE, LGATE and PHASE)
away from sensitive small signal nodes since these
nodes are fast moving signals. Therefore, keep traces to
these nodes as short as possible.
The traces from the gate drivers to the MOSFETs
(UGATE1, LGATE1, UGATE2, LGATE2) should be short
and wide.
Decoupling capacitor, compensation component, the
resistor dividers, boot capacitors, and SS capacitors
should be close their pins.
The input capacitor should be near the drain of the
upper MOSFET; the output capacitor should be near the
loads. The input capacitor GND should be close to the
output capacitor GND and the lower MOSFET GND.
The drain of the MOSFETs (VIN and phase nodes)
should be a large plane for heat sinking.
Figure 10. Layout Guidelines
V
IN
V
OUT
Q1
L1
C
IN
APW7158
L
O
A
D
BOOT
VCC12
SS
FB
GND
C
SS
C
VCC
C
BOOT
Q2
C
OUT
VCC
LG
UG
PGND
C
VCC12
VREF
C
VREF
REFOUT
C
REFOUT


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