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TMC2250A Datasheet(PDF) 10 Page - Fairchild Semiconductor |
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TMC2250A Datasheet(HTML) 10 Page - Fairchild Semiconductor |
10 / 23 page PRODUCT SPECIFICATION TMC2250A 10 REV. 1.0.2 10/25/00 9-Tap FIR Filter Mode (01) The architecture for this configuration is shown in Figure 4. The user loads the desired coefficient set, presents input data to ports A and B simultaneously (most applications will wire the A and B inputs together), and receives the resulting 9- sample response, half-LSB rounded to 16 bits, 5 to 13 clock cycles later. A new output data word is available every clock cycle. The figure shows that the input data are automatically right- shifted by one position through the row of multiplier input registers on every clock in anticipation of a new input data word. CASOUT(13) = A(9)KA3(9)+A(8)KA2(8)+A(7)KA1(7) +B(6)KB3(9)+B(5)KB2(8)+B(4)KB1(7) +B(3)KC3(9)+B(2)KC2(8)+B(1)KC1(7) +CASIN(10) Latency: Impulse in to center of 9-tap response =9 registers. Cascade In to Cascade Out=4 registers. Figure 3. 9-Tap FIR Filter Impulse Response (Mode 01) CLK 1 01 10 11 1.0 01 Q13 Q13 KC1 KC2 KC3 KB1 KB2 KB3 KA1 KA2 KA3 K_1 K_2 K_3 2 3 4 5 6 7 8 9 10 11 12 13 15 16 17 14 CWE KA, KB, KC DATA IN A, B MODE CONTROL CASIN CASOUT |
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