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AD7475ARZ Datasheet(PDF) 8 Page - Analog Devices |
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AD7475ARZ Datasheet(HTML) 8 Page - Analog Devices |
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8 / 24 page  AD7475/AD7495 Rev. B | Page 8 of 24 TIMING EXAMPLE 1 With fSCLK = 20 MHz and a throughput of 1 MSPS, the cycle time is t2 + 12.5(1/fSCLK) + tACQ = 1 μs. With t2 = 10 ns min, tACQ is 365 ns. The 365 ns satisfies the requirement of 300 ns for tACQ. In Figure 3, tACQ comprises 2.5(1/fSCLK) + t8 + tQUIET, where t8 = 45 ns. This allows a value of 195 ns for tQUIET, satisfying the minimum requirement of 100 ns. TIMING EXAMPLE 2 With fSCLK = 5 MHz and a throughput of 315 KSPS, the cycle time is t2 + 12.5(1/fSCLK) + tACQ = 3.174 μs. With t2 = 10 ns min, tACQ is 664 ns. The 664 ns satisfies the requirement of 300 ns for tACQ. In Figure 3, tACQ comprises 2.5(1/fSCLK) + t8 + tQUIET, where t8 = 45 ns. This allows a value of 119 ns for tQUIET, satisfying the minimum requirement of 100 ns. As in this example and with other slower clock values, the signal may already be acquired before the conversion is complete, but it is still necessary to leave 100 ns minimum tQUIET between conversions. In Example 2, the signal should be fully acquired at approximately Point C in Figure 3. SCLK 1 5 13 15 SDATA FOUR LEADING ZEROS THREE-STATE t4 2 3 16 t5 t3 tQUIET tCONVERT t2 THREE-STATE DB11 DB10 DB2 DB0 t6 t7 t8 14 0 0 0 0 B DB1 CS 4 Figure 2. Serial Interface Timing Diagram SCLK 1 5 13 15 2 3 16 t5 tQUIET tCONVERT t2 t6 t8 14 B 45ns tACQUISITION 12.5 (1/fSCLK) 10ns 1/THROUGHPUT C CS 4 Figure 3. Serial Interface Timing Example 200 μA IOL 200 μA IOH CL 50pF TO OUTPUT PIN 1.6V Figure 4. Load Circuit for Digital Output Timing Specifications |
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