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MC9S12DG256MPVE Datasheet(PDF) 1 Page - Freescale Semiconductor, Inc |
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MC9S12DG256MPVE Datasheet(HTML) 1 Page - Freescale Semiconductor, Inc |
1 / 14 page MC9S12D-FamilyPP Rev 6.1, 23-Oct-02 MC9S12D-Family Product Brief 16-Bit Microcontroller Designed for automotive multiplexing applications, members of the MC9S12D-Family of 16 bit Flash- based microcontrollers are fully pin compatible and enable users to choose between different memory and peripheral options for scalable designs. All MC9S12D-Family members are composed of standard on-chip peripherals including a 16-bit central processing unit (CPU12), up to 512K bytes of Flash EEPROM, 14K bytes of RAM, 4K bytes of EEPROM, two asynchronous serial communications interfaces (SCI), three serial peripheral interfaces (SPI), IIC-bus, an enhanced capture timer (ECT), two 8-channel 10-bit analog-to-digital converters (ADC), an eight-channel pulse-width modulator (PWM), J1850 interface and up to five CAN 2.0 A, B software compatible modules (MSCAN12). System resource mapping, clock generation, interrupt control and bus interfacing are managed by the system integration module (SIM). The MC9S12D-Family has full 16-bit data paths throughout, however, the external bus can operate in an 8-bit narrow mode so single 8-bit wide memory can be interfaced for lower cost systems. The inclusion of a PLL circuit allows power consumption and performance to be adjusted to suit operational requirements. In addition to the I/O ports available in each module, up to 22 I/O ports are available with interrupt capability allowing Wake-Up from STOP or WAIT mode. Features NOTE Not all features listed here are available in all configurations. Additional information about D and B family inter-operability is given in: EB386 “HCS12 D-Family Compatibility Considerations” and EB388 “Using the HCS12 D-Family as a development platform for the HCS12 B family” • 16-bit CPU12 — Upward compatible with M68HC11 instruction set — Interrupt stacking and programmer’s model identical to M68HC11 — HCS12 Instruction queue — Enhanced indexed addressing • Multiplexed bus — Single chip or expanded — 16 address/16 data wide or 16 address/8 data narrow modes — External address space 1MByte for Data and Program space (112 pin package only) • Wake-up interrupt inputs depending on the package option — 8-bit port H — 2-bit port J1:0 — 2-bit port J7:6 shared with IIC, CAN4 and CAN0 module — 8-bit port P shared with PWM or SPI1,2 • Memory options — 32K, 64K, 128K, 256K, 512K Byte Flash EEPROM — 1K, 2K, 4K Byte EEPROM — 2K, 4K, 8K, 12K, 14K Byte RAM Freescale Semiconductor, Inc. For More Information On This Produ Go to: www.freescale.com |
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