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LT1720IDD Datasheet(PDF) 17 Page - Linear Technology |
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LT1720IDD Datasheet(HTML) 17 Page - Linear Technology |
17 / 28 page ![]() LT1720/LT1721 17 17201fc Timing Skews For a number of reasons, the LT1720/LT1721’s superior timing specifications make them an excellent choice for applications requiring accurate differential timing skew. The comparators in a single package are inherently well matched, with just 300ps ΔtPDtypical.Monolithicconstruc- tion keeps the delays well matched vs supply voltage and temperature. Crosstalk between the comparators, usually a disadvantage in monolithic duals and quads, has minimal effect on the LT1720/LT1721 timing due to the internal hysteresis, as described in the Speed Limits section. The circuits of Figure 11 show basic building blocks for differential timing skews. The 2.5k resistance interacts with the 2pF typical input capacitance to create at least ±4ns delay, controlled by the potentiometer setting. A differential and a single-ended version are shown. In the differential configuration, the output edges can be smoothly scrolled through Δt = 0 with negligible interaction. 3ns Delay Detector It is often necessary to measure comparative timing of pulse edges in order to determine the true synchronicity of clock and control signals, whether in digital circuitry or in high speed instrumentation. The circuit in Figure 12 APPLICATIONS INFORMATION is a delay detector which will output a pulse when signals X and Y are out of sync (specifically, when X is high and Y is low). Note that the addition of an identical circuit to detect the opposite situation (X low and Y high) allows for full skew detection. Comparators U1A and U1B clean up the incoming signals and render the circuit less sensitive to input levels and slew rates. The resistive divider network provides level shifting for the downstream comparator’s common mode input range, as well as offset to keep the output low except during a decisive event. When the upstream comparator’s outputs can overcome the resistively generated offset (and hysteresis), comparator U1C performs a Boolean “X*_Y” function and produces an output pulse (see Figure 13). The circuit will give full output response with input delays down to 3ns and partial output response with input delays down to 1.8ns. Capacitor C1 helps ensure that an imbal- ance of parasitic capacitances in the layout will not cause common mode excursions to result in differential mode signal and false outputs.1 1 Make sure the input levels at X and Y are not too close to the 0.5V threshold set by the R8–R9 divider. If you are still getting false outputs, try increasing C1 to 10pF or more. You can also look for the problem in the impedance balance (R5 || R6 = R7) at the inputs of U1C. Increasing the offset by lowering R5 will help reject false outputs, but R7 should also be lowered to maintain impedance balance. For ease of design and parasitic matching, R7 can be replaced by two parallel resistors equal to R5 and R6. LT1720 DIFFERENTIAL 4ns RELATIVE SKEW CIN CIN CIN CIN VREF 2.5k 2.5k INPUT LT1720 0ns TO 4ns SINGLE-ENDED DELAY CIN CIN 17201 F11 VREF INPUT CIN CIN – + – + Figure 11. Building Blocks for Timing Skew Generation with the LT1720 |
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