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LT1720IDD Datasheet(PDF) 14 Page - Linear Technology |
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LT1720IDD Datasheet(HTML) 14 Page - Linear Technology |
14 / 28 page ![]() LT1720/LT1721 14 17201fc Speed Limits The LT1720/LT1721 comparators are intended for high speed applications, where it is important to understand a few limitations. These limitations can roughly be divided into three categories: input speed limits, output speed limits, and internal speed limits. There are no significant input speed limits except the shunt capacitance of the input nodes. If the 2pF typical input nodes are driven, the LT1720/LT1721 will respond. The output speed is constrained by two mechanisms, the first of which is the slew currents available from the output transistors. To maintain low power quiescent op- eration, the LT1720/LT1721 output transistors are sized to deliver 25mA to 45mA typical slew currents. This is sufficient to drive small capacitive loads and logic gate inputs at extremely high speeds. But the slew rate will slow dramatically with heavy capacitive loads. Because the propagation delay (tPD) definition ends at the time the output voltage is halfway between the supplies, the fixed slew current actually makes the LT1720/LT1721 faster at 3V than 5V with 20mV of input overdrive. Another manifestation of this output speed limit is skew, the difference between tPDLH and tPDHL. The slew currents of the LT1720/LT1721 vary with the process variations of the PNP and NPN transistors, for rising edges and falling edges respectively. The typical 0.5ns skew can have either polarity, rising edge or falling edge faster. Again, the skew will increase dramatically with heavy capacitive loads. The skews of comparators in a single package are corre- lated, but not identical. Besides some random variability, there is a small (100ps to 200ps) systematic skew due to physical parasitics of the packages. For the LT1720 SO-8, comparator A, whose output is adjacent to the VCC pin, will have a relatively faster rising edge than comparator B. Likewise, comparator B, by virtue of an output adjacent to the ground pin will have a relatively faster falling edge. Similar dependencies occur in the LT1721 S16, while the systemic skews in the smaller MSOP and SSOP packages are half again as small. Of course, if the capacitive loads on the two comparators of a single package are not identical, the differential timing will degrade further. APPLICATIONS INFORMATION The second output speed limit is the clamp turnaround. The LT1720/LT1721 output is optimized for fast initial response, with some loss of turnaround speed, limiting the toggle frequency. The output transistors are idled in a low power state once VOH or VOL is reached by detecting the Schottky clamp action. It is only when the output has slewed from the old voltage to the new voltage, and the clamp circuitry has settled, that the idle state is reached and the output is fully ready to transition again. This clamp turnaround time is typically 8ns for each direction, resulting in a maximum toggle frequency of 62.5MHz, or a 125MB data rate. With higher frequencies, dropout and runt pulses can occur. Increases in capacitive load will increase the time needed for slewing due to the limited slew currents and the maximum toggle frequency will decrease further. For higher toggle frequency applications, refer to the LT1715, whose output stage can toggle at 150MHz typical. The internal speed limits manifest themselves as disper- sion. All comparators have some degree of dispersion, defined as a change in propagation delay versus input overdrive. The propagation delay of the LT1720/LT1721 will vary with overdrive, from a typical of 4.5ns at 20mV overdrive to 7ns at 5mV overdrive (typical). The LT1720/ LT1721’s primary source of dispersion is the hysteresis stage. As a change of polarity arrives at the gain stage, the positive feedback of the hysteresis stage subtracts from the overdrive available. Only when enough time has elapsed for a signal to propagate forward through the gain stage, backwards through the hysteresis stage and forward through the gain stage again, will the output stage receive the same level of overdrive that it would have received in the absence of hysteresis. With 5mV of overdrive, the LT1720/LT1721 are faster with a 5V supply than with a 3V supply, the opposite of what is true with 20mV overdrive. This is due to the internal speed limit, because the gain stage is faster at 5V than 3V due primarily to the reduced junction capacitances with higher reverse voltage bias. In many applications, as shown in the following examples, there is plenty of input overdrive. Even in applications providing low levels of overdrive, the LT1720/LT1721 are fast enough that the absolute dispersion of 2.5ns (= 7 – 4.5) is often small enough to ignore. |
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