ICM7555_2

© NXP B.V. 2009. All rights reserved.

Product data sheet

Rev. 02 — 3 August 2009

12 of 22

NXP Semiconductors

ICM7555

General purpose CMOS timer

11.4 Astable operation

If the circuit is connected as shown in Figure 15, it will trigger itself and free run as a

⁄

2

⁄

supply voltage, the frequency of oscillation is independent of the supply voltage.

(1)

(2)

11.5 Monostable operation

In this mode of operation, the timer functions as a one-shot. Initially, the external

capacitor (C) is held discharged by a transistor inside the timer. Upon application of a

negative pulse to pin 2, TRIGGER, the internal flip-flop is set, which releases the

low-impedance on DISCHARGE; the external capacitor charges and drives the OUTPUT

HIGH. The voltage across the capacitor increases exponentially with a time constant

flip-flop, which in turn discharges the capacitor rapidly and also drives the OUTPUT to its

LOW state. TRIGGER must return to a HIGH state before the OUTPUT can return to a

LOW state.

Fig 15. Astable operation

f

1.38

R

A

2R

B

+

() C

×

--------------------------------------

=

δ

R

A

R

B

+

R

A

2R

B

+

-----------------------

=

GND

TRIGGER

OUTPUT

RESET

1

2

3

4

C

RB

RA

OUTPUT

DISCHARGE

THRESHOLD

CONTROL_VOLTAGE

8

7

6

5

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