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CD4070BM96G4 Datasheet(PDF) 3 Page - Texas Instruments |
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CD4070BM96G4 Datasheet(HTML) 3 Page - Texas Instruments |
3 / 30 page 3 FIGURE 1. SCHEMATIC DIAGRAM FOR CD4070B (1 OF 4 IDENTICAL GATES) CD4070B TRUTH TABLE (1 OF 4 GATES) AB J 000 101 011 110 NOTE: 1 = High Level 0 = Low Level J = A ⊕ B VDD VSS VSS VDD VDD VSS VSS VDD p n p n p n p p n p n J 3(4,10,11) B † 2(5,9,12) A † 1(6,8,13) † INPUTS PROTECTED BY CMOS PROTECTION NETWORK FIGURE 2. SCHEMATIC DIAGRAM FOR CD4077B (1 OF 4 IDENTICAL GATES) CD4077B TRUTH TABLE (1 OF 4 GATES) AB J 001 100 010 111 NOTE: 1 = High Level 0 = Low Level J = A ⊕ B VDD VSS VSS VDD VDD VSS VSS VDD p n p n p n p n p n J 3(4,10,11) B † 2(5,9,12) A † 1(6,8,13) † INPUTS PROTECTED BY CMOS PROTECTION NETWORK n CD4070B, CD4077B |
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