1

Data sheet acquired from Harris Semiconductor

SCHS055E

Features

• High-Voltage Types (20V Rating)

• CD4070B - Quad Exclusive-OR Gate

• CD4077B - Quad Exclusive-NOR Gate

• Medium Speed Operation

• 100% Tested for Quiescent Current at 20V

• Standardized Symmetrical Output Characteristics

• 5V, 10V and 15V Parametric Ratings

• Maximum Input Current of 1

µA at 18V Over Full

Package Temperature Range

• Noise Margin (Over Full Package Temperature Range)

• Meets All Requirements of JEDEC Standard No. 13B,

“Standard Specifications for Description of ‘B’ Series

CMOS Devices

Applications

• Logical Comparators

• Adders/Subtractors

• Parity Generators and Checkers

Description

The Harris CD4070B contains four independent Exclusive-

OR gates. The Harris CD4077B contains four independent

Exclusive-NOR gates.

The CD4070B and CD4077B provide the system designer

with a means for direct implementation of the Exclusive-OR

and Exclusive-NOR functions, respectively.

NOTE: When ordering, use the entire part number. The suffixes 96

and R denote tape and reel. The suffix T denotes a small-quantity

reel of 250.

Ordering Information

PART NUMBER

TEMP. RANGE

PACKAGE

CD4070BE

-55 to 125

14 Ld PDIP

CD4070BF3A

-55 to 125

14 Ld CERDIP

CD4070BM

-55 to 125

14 Ld SOIC

CD4070BMT

-55 to 125

14 Ld SOIC

CD4070BM96

-55 to 125

14 Ld SOIC

CD4070BNSR

-55 to 125

14 Ld SOP

CD4070BPW

-55 to 125

14 Ld TSSOP

CD4070BPWR

-55 to 125

14 Ld TSSOP

CD4077BE

-55 to 125

14 Ld PDIP

CD4077BF3A

-55 to 125

14 Ld CERDIP

CD4077BM

-55 to 125

14 Ld SOIC

CD4077BMT

-55 to 125

14 Ld SOIC

CD4077BM96

-55 to 125

14 Ld SOIC

CD4077BNSR

-55 to 125

14 Ld SOP

CD4077BPW

-55 to 125

14 Ld TSSOP

CD4077BPWR

-55 to 125

14 Ld TSSOP

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

Copyright

CD4070B,

CD4077B

CMOS Quad Exclusive-OR

and Exclusive-NOR Gate

[ /Title

(CD40

70B,

CD407

7B)

/Sub-

ject

(CMO

S Quad

Exclu-

sive-

OR

and

Exclu-

sive-

NOR

Gate)

/Autho

r ()

/Key-

words

(Har-

ris

Semi-

con-

ductor,

CD400

0,

metal

gate,

CMOS

, pdip,

cerdip,

mil,

January 1998 - Revised September 2003