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DAC8534IPWRG4 Datasheet(PDF) 13 Page - Texas Instruments |
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DAC8534IPWRG4 Datasheet(HTML) 13 Page - Texas Instruments |
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13 / 24 page  13 DAC8534 SBAS254D www.ti.com D23 D22 D21 D20 D19 D18 D17 D16 A1 A0 Load 1 Load 0 Don’t Care DAC Sel 1 DAC Sel 0 PD0 This address selects 1 of 4 possible devices on a single SPI data bus based on each device’s address pin(s) state. 0 0 X 0 0 0 Write To Buffer A w/Data 0 0 X 0 1 0 Write To Buffer B w/Data 0 0 X 1 0 0 Write To Buffer C w/Data 0 0 X 1 1 0 Write To Buffer D w/Data Write To Buffer (selected by DB17 and DB18) w/Power-Down Command Write To Buffer w/Data and Load DAC (selected by DB17 and DB18) Write To Buffer w/Power-Down Command and Load DAC (selected by DB17 and DB18) 10 X Write To Buffer w/Data (selected by DB17 and DB18) and Load All DACs Write To Buffer w/Power-Down Command (selected by DB17 and DB18) and Load All DACs X X 1 1 X 0 X X Load All DACs, All Device, and All Buffers with Stored Data X X 1 1 X 1 X 0 Write To All Devices and Load All Dacs, with SR Data Write To All Devices w/Power-Down Command in SR SCLK SYNC DIN Invalid Write-Sync Interrupt: SYNC HIGH Before 24th Falling Edge Valid Write-Buffer/DAC Update: SYNC HIGH After 24th Falling Edge DB23 DB22 12 12 DB0 DB23 DB22 DB1 DB0 24th Falling Edge 24th Falling Edge FIGURE 4. Interrupt and Valid SYNC Timing. D15 D14 D13-D0 MSB MSB-1 MSB-2...LSB single 16-bit DAC with power-down circuitry, a temporary storage register (TR), and a DAC register (DR). TR and DR are both 18-bit wide. Two MSBs represent power-down condition and 16LSBs represent data for TR and DR. By adding bits 17 and 18 to TR and DR, a power-down condition can be temporarily stored and used just like data. Internal circuits ensure that DB15 and DB14 get transfered to TR17 and TR16 (DR17 and DR16), when DB16 = 1. The DAC8534 treats the power-down condition like data and all the operational modes are still valid for power-down. It is possible to broadcast a power-down condition to all the DAC8534s in a system, or it is possible to simultaneously power-down a channel while updating data on other channels. DB16, DB15, and DB14 = 100 represent a power-down condition with Hi-Z output impedance for a selected channel. Same is true for 111. 101 represents a power-down condition with 1k output impedance and 110 represents a power-down condition with 100k output impedance. TABLE II. Control Matrix. DESCRIPTION (A0 and A1 should correspond to the package address set via pins 13 and 14.) See Below 0/1 0/1 (00, 01, 10, or 11) (00, 01, 10, or 11) (00, 01, 10, or 11) (00, 01, 10, or 11) (00, 01, 10, or 11) 01 X 10 X Data Data Data Data Data Data Data (see Table I) 0 (see Table I) 0 (see Table I) 0 (see Table I) 0 1 0 1 XX 1 1 X 1 X 1 X When both bits are set to 0 or 1, the device enters a high- impedance state with a typical power consumption of 3pA at 5V. For the two low impedance output modes, however, the supply current falls to 100nA at 5V (50nA at 3V). Not only does the supply current fall, but the output stage is also internally switched from the output of the amplifier to a resistor network of known values. This has the advantage that the output impedance of the device is known while it is in power-down mode. There are three different options for power-down: the output is connected internally to GND through a 1k Ω resistor, a 100k Ω resistor, or it is left open-circuited (High-Impedance). The output stage is illustrated in Figure 5. All analog circuitry is shut down when the power-down mode is activated. Each DAC will exit power-down when PD0 is set to 0, new data is written to the Data Buffer, and the DAC channel receives a “Load” command. The time to exit power- down is typically 2.5 µs for AV DD = 5V and 5µs for AVDD = 3V (see the Typical Characteristics). Broadcast Modes 01 X 0 1 00 X (Address Select) |
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