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DAC8534IPWRG4 Datasheet(PDF) 12 Page - Texas Instruments |
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DAC8534IPWRG4 Datasheet(HTML) 12 Page - Texas Instruments |
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12 / 24 page  DAC8534 12 SBAS254D www.ti.com A1 A0 LD1 LD0 X DAC Select 1 DAC Select 0 PD0 D15 D14 D13 D12 D11 D10 D9D8D7 D6D5D4D3 D2D1 D0 DB11 DB0 FIGURE 3. DAC8534 Data Input Register Format. DB23 DB12 reference to shift the incoming logic HIGH levels to AVDD. IOVDD is ensured to operate from 2.7V to 5.5V regardless of the AVDD voltage, which ensures compatibility with various logic families. Although specified down to 2.7V, IOVDD will operate at as low as 1.8V with degraded timing and tempera- ture performance. For lowest power consumption, logic VIH levels should be as close as possible to IOVDD, and logic VIL levels should be as close as possible to GND voltages. INPUT SHIFT REGISTER The input shift register (SR) of the DAC8534 is 24 bits wide, as shown in Figure 3, and is made up of 8 control bits (DB16-DB23) and 16 data bits (DB0-DB15). The first two control bits (DB22 and DB23) are the address match bits. The DAC8534 offers additional hardware-enabled addressing capability allowing a single host to talk to up to four DAC8534s through a single SPI bus without any glue logic, enabling up to 16-channel operation. The state of DB23 should match the state of pin A1; similarly, the state of DB22 should match the state of pin A0. If there is no match, the control command and the data (DB21...DB0) are ignored by the DAC8534. That is, if there is no match, the DAC8534 is not addressed. Address matching can be overrid- den by the broadcast update, as will be explained. LD 1 (DB20) and LD 0 (DB21) control the updating of each analog output with the specified 16-bit data value or power- down command. Bit DB19 is a “Don’t Care” bit which does not affect the operation of the DAC8534 and can be 1 or 0. The DAC Channel Select Bits (DB17, DB18) control the destination of the data (or power-down command) from DAC A through DAC D. The final control bit, PD0 (DB16), selects the power- down mode of the DAC8534 channels. The DAC8534 also supports a number of different load com- mands. The load commands include broadcast commands to address all the DAC8534s on an SPI bus. The load commands can be summarized as follows: DB21 = 0 and DB20 = 0: Single-channel store. The temporary register (data buffer) corresponding to a DAC selected by DB18 and DB17 is updated with the contents of SR data (or power-down). DB21 = 0 and DB20 = 1: Single-channel update. The tempo- rary register and DAC register corresponding to a DAC se- lected by DB18 and DB17 are updated with the contents of SR data (or power-down). DB21 = 1 and DB20 = 0: Simultaneous update. A channel selected by DB18 and DB17 gets updated with the SR data, and simultaneously, all the other channels get updated with previous stored data (or power-down). DB21 = 1 and DB20 = 1: Broadcast update. All the DAC8534s on the SPI bus respond, regardless of address matching. If DB18 = 0, then SR data gets ignored, all channels from all DAC8534s get updated with previously stored data (or power- down). If DB18 = 1, then SR data (or power-down) updates all channels of all DAC8534s in the system. This broadcast update feature allows the simultaneous update of up to 16 channels. Power-down/data selection is as follows: DB16 is a power-down flag. If this flag is set, then DB15 and DB14 select one of the four power-down modes of the device as described in Table I. If DB16 = 1, DB15 and DB14 no longer represent the two MSBs of data, they represent a power-down condition described in Table I. Similar to data, power-down conditions can be stored at the temporary registers of each DAC. It is possible to update DACs simultaneously either with data, power-down, or a combination of both. Please refer to Table II for more information. PD0 (DB16) PD1 (DB15) PD2 (DB14) OPERATING MODE 1 0 0 Output High Impedance 1 0 1 Output Typically 1k Ω to GND 1 1 0 Output Typically 100k Ω to GND 1 1 1 Output High Impedance TABLE I. DAC8534 Power-Down Modes. SYNC INTERRUPT In a normal write sequence, the SYNC line is kept LOW for at least 24 falling edges of SCLK and the addressed DAC register is updated on the 24th falling edge. However, if SYNC is brought HIGH before the 24th falling edge, it acts as an interrupt to the write sequence; the shift register is reset and the write sequence is discarded. Neither an update of the data buffer contents, DAC register contents, nor a change in the operating mode occurs (see Figure 4). POWER-ON RESET The DAC8534 contains a power-on reset circuit that con- trols the output voltage during power-up. On power-up, the DAC registers are filled with zeros and the output voltages are set to zero-scale; they remain there until a valid write sequence and load command is made to the respective DAC channel. This is useful in applications where it is important to know the state of the output of each DAC output while the device is in the process of powering up. No device pin should be brought high before power is applied to the device. POWER-DOWN MODES The DAC8534 utilizes four modes of operation. These modes are accessed by setting three bits (PD2, PD1, and PD0) in the shift register and performing a “Load” action to the DACs. The DAC8534 offers a very flexible power-down interface based on channel register operation. A channel consists of a |
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