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DAC8534IPWRG4 Datasheet(PDF) 18 Page - Texas Instruments |
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DAC8534IPWRG4 Datasheet(HTML) 18 Page - Texas Instruments |
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18 / 24 page  DAC8534 18 SBAS254D www.ti.com The output voltage for any input code can be calculated as follows: VX V D RR R V R R OUT REF REF =• • + • 65536 12 1 2 1 – where D represents the input code in decimal (0–65535). With VREF = 5V, R1 = R2 = 10kΩ: VX D V OUT = • 10 65536 5 – This is an output voltage range of ±5V with 0000 H corre- sponding to a –5V output and FFFFH corresponding to a +5V output. Similarly, using VREF = 2.5V, a ±2.5V output voltage range can be achieved. LAYOUT A precision analog component requires careful layout, ad- equate bypassing, and clean, well-regulated power supplies. The DAC8534 offers single-supply operation, and it will often be used in close proximity with digital logic, microcontrollers, microprocessors, and digital signal processors. The more digital logic present in the design and the higher the switch- ing speed, the more difficult it will be to keep digital noise from appearing at the output. Due to the single ground pin of the DAC8534, all return currents, including digital and analog return currents for the DAC, must flow through a single point. Ideally, GND would be connected directly to an analog ground plane. This plane would be separate from the ground connection for the digital components until they were connected at the power-entry point of the system. The power applied to AVDD should be well regulated and low noise. Switching power supplies and DC/DC converters will often have high-frequency glitches or spikes riding on the output voltage. In addition, digital components can create similar high-frequency spikes as their internal logic switches states. This noise can easily couple into the DAC output voltage through various paths between the power connec- tions and analog output. As with the GND connection, AVDD should be connected to a positive power-supply plane or trace that is separate from the connection for digital logic until they are connected at the power-entry point. In addition, a 1 µF to 10µF capacitor in parallel with a 0.1 µF bypass capacitor is strongly recom- mended. In some situations, additional bypassing may be required, such as a 100 µF electrolytic capacitor or even a “Pi” filter made up of inductors and capacitors—all designed to essentially low-pass filter the supply, removing the high- frequency noise. Up to four DAC8534 devices can be used on a single SPI bus without any glue logic to create a high channel count solu- tion. Special attention is required to avoid digital signal integrity problems when using multiple DAC8534s on the same SPI bus. Signal integrity of SYNC, SCLK, and DIN lines will not be an issue as long as the rise times of these digital signals are longer than six times the propagation delay between any two DAC8534 devices. Propagation speed is approximately six inches/ns on standard PCBs. Therefore, if the digital signal risetime is 1ns, the distance between any two DAC8534 devices is recommended not to exceed 1 inch. If the DAC8534s have to be further apart on the PCB, the signal rise times should be reduced by placing series resis- tors at the drivers for SYNC, SCLK, and DIN lines. If the largest distance between any two DAC8534s has to be six inches, the risetime should be reduced to 6ns with an RC network formed by the series resistor at the digital driver and the total trace and input capacitance on the PCB. |
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