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TMP121AIDBVRG4 Datasheet(PDF) 6 Page - Texas Instruments |
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TMP121AIDBVRG4 Datasheet(HTML) 6 Page - Texas Instruments |
6 / 18 page TMP121 TMP123 SBOS273C − JUNE 2003 − REVISED FEBRUARY 2005 www.ti.com 6 0.25s 0.5s 50 µA(active) 20 µA(idle) Figure 2. Conversion Time and Period The serial data of the TMP121 and TMP123 consists of 12-bit plus sign temperature data followed by a confirmation bit and two high impedance bits. Data is transmitted in Binary Two’s Complement format. Figure 3 describes the output data of the TMP121 and TMP123. Timing Diagrams The TMP121 and TMP123 are SPI-compatible. Figure 4 and Figure 5 describe the various timing requirements, with parameters defined in Table 3. PARAMETER MIN MAX UNITS SCK Period t1 100 ns SCK Falling Edge to Output Data Delay t2 30 ns CS to Rising Edge SCK Set-Up Time t3 40 ns CS to Output Data Delay t4 30 ns CS Rising Edge to Output High Impedance t5 30 ns Table 3. Timing Description SO/I SCK CS Z Z 1 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 Z Figure 3. Data READ SCK CS SO t 1 t 3 t 2 t 4 Figure 4. Output Data Timing Diagram SCK CS SO t 5 t 5 SCK CS SO Figure 5. High Impedance Output Timing Diagram |
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