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AD5300BRT-500RL7 Datasheet(PDF) 8 Page - Analog Devices |
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AD5300BRT-500RL7 Datasheet(HTML) 8 Page - Analog Devices |
8 / 13 page ![]() AD5300 –8– REV. GENERAL DESCRIPTION D/A Section The AD5300 DAC is fabricated on a CMOS process. The archi- tecture consists of a string DAC followed by an output buffer amplifier. Since there is no reference input pin, the power supply (VDD) acts as the reference. Figure 20 shows a block diagram of the DAC architecture. VDD VOUT GND RESISTOR STRING REF (+) REF (–) OUTPUT AMPLIFIER DAC REGISTER Figure 20. DAC Architecture Since the input coding to the DAC is straight binary, the ideal output voltage is given by VOUT =V DD × D 256 where D = decimal equivalent of the binary code that is loaded to the DAC register; D can range from 0 to 255. Resistor String The resistor string section is shown in Figure 21. It is simply a string of resistors, each of value R. The code loaded to the DAC register determines at which node on the string the voltage is tapped off to be fed into the output amplifier. The voltage is tapped off by closing one of the switches connecting the string to the amplifier. Because it is a string of resistors, it is guaran- teed monotonic. R R TO OUTPUT AMPLIFIER R R R Figure 21. Resistor String Output Amplifier The output buffer amplifier is capable of generating rail-to-rail voltages on its output, which gives an output range of 0 V to VDD. It is capable of driving a load of 2 k Ω in parallel with 1000 pF to GND. The source and sink capabilities of the output amplifier can be seen in Figures 8 and 9. The slew rate is 1 V/ µs with a half-scale settling time of 4 µs with the output loaded. SERIAL INTERFACE The AD5300 has a 3-wire serial interface ( SYNC, SCLK, and DIN), which is compatible with SPI, QSPI, and MICROWIRE interface standards as well as most DSPs. See Figure 1 for a timing diagram of a typical write sequence. The write sequence begins by bringing the SYNC line low. Data from the DIN line is clocked into the 16-bit shift register on the falling edge of SCLK. The serial clock frequency can be as high as 30 MHz, making the AD5300 compatible with high speed DSPs. On the 16th falling clock edge, the last data bit is clocked in and the programmed function is executed (i.e., a change in DAC register contents and/or a change in the mode of operation). At this stage, the SYNC line may be kept low or be brought high. In either case, it must be brought high for a minimum of 33 ns (VDD = 3.6 V to 5.5 V) or 50 ns (VDD = 2.7 V to 3.6 V) before the next write sequence so that a falling edge of SYNC can initiate the next write sequence. Since the SYNC buffer draws more current when VIN = 2.4 V than it does when VIN = 0.8 V, SYNC should be idled low between write sequences for even lower power operation of the part. As previously men- tioned, however, it must be brought high again just before the next write sequence. Input Shift Register The input shift register is 16 bits wide (see Figure 22). The first two bits are Don’t Cares. The next two are control bits that control which mode of operation the part is in (normal mode or any one of three power-down modes). There is a more complete description of the various modes in the Power-Down Modes section. The next eight bits are the data bits. These are transferred to the DAC register on the 16th falling edge of SCLK. Finally, the last four bits are Don’t Cares. DB0 (LSB) DB15 (MSB) 00 NORMAL OPERATION 01 1k TO GND 10 100k TO GND 11 THREE-STATE POWER-DOWN MODES DATA BITS XX PD1 PD 0 D7 D6 D5D4D3 D2 D1 D0 X X X X Figure 22. Input Register Contents D |
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