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NCP5230MNTWG Datasheet(PDF) 2 Page - ON Semiconductor |
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NCP5230MNTWG Datasheet(HTML) 2 Page - ON Semiconductor |
2 / 12 page ![]() NCP5230 http://onsemi.com 2 Figure 1. NCP5230 BLOCK DIAGRAM 4 5 3 1 2 16 13 12 8 9 BOOT UG LX VCCP LG GND CSP CSN/VO COMP FB Control Logic, Protection, RAMP Generator and PWM Logic + − + − CDIFF UVLO Control − + + − VREF*75% VREF*125% UVP OVP OSC Error Amplifier Current Sense Amplifier + − VREF*50% OVP, UNLATCHED 0.8V 11 10 VSEN FBG 15 7 SYNC 14 ROSC/EN Programmable OSC 6 1.24V 2.2 W Over Current Detector PIN DESCRIPTIONS Pin No. Symbol Description 1 VCCP Power supply for bottom gate MOSFET drivers 2 LG Bottom gate MOSFET driver pin 3 LX Switch node 4 BOOT Supply rail for the floating top gate driver 5 UG Top gate MOSFET driver pin 6 PGOOD Power Good. It is an open−drain output, set free after SS (with 3x clock delay) as long as the output voltage monitored through VSEN is within specifications. 7 SYNC Synchronization Pin. The controller synchronizes on the falling edge of a square wave provided to this pin. Short to GND if not used. 8 COMP Output of the error amplifier 9 FB Inverting input to the error amplifier 10 VSEN Output Voltage Sense 11 FBG Remote Ground Sense 12 CSN/VO Inductor differential sense inverting input 13 CSP Inductor differential sense non−inverting input 14 ROSC/EN Programs the switching frequency; EN: Pull−low to disable the device 15 VCC Supply rail for the controller internal circuitry 16 GND Ground reference THERMAL PAD Connects with the silicon substrate for good thermal contact with the PCB. Connect to GND plane. |
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