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IA186ES Datasheet(PDF) 98 Page - InnovASIC, Inc |
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IA186ES Datasheet(HTML) 98 Page - InnovASIC, Inc |
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98 / 154 page  IA186ES/IA188ES Data Sheet 8-Bit/16-Bit Microcontrollers November 15, 2011 IA211050902-19 http://www.innovasic.com UNCONTROLLED WHEN PRINTED OR COPIED Customer Support: Page 98 of 154 1-888-824-4184 ® Bits [15–4]—Reserved. Set to 0. Bit [3]—MSK Mask → Any of the interrupt sources may cause an interrupt if the MSK bit is 0. The interrupt sources cannot cause an interrupt if the MSK bit is 1. The Interrupt Mask Register has a duplicate of this bit. Bit [2–0]—PR [2–0] Priority → These bits define the priority of the serial port interrupts in relation to other interrupt signals. The interrupt priority is the lowest at 7 upon reset. The values of PR2–PR0 are shown above. 5.1.40 DMA1CON/INT6CON (036h) and DMA0CON/INT5CON (034h) (Master Mode) DMA and INTerrupt CONtrol Register. The DMA0 and DMA1 interrupts have interrupt type 0ah and 0bh, respectively. These pins are configured as external interrupts or DMA requests in the respective DMA Control register. The value of these registers is 000Fh at reset (see Table 61). Table 61. DMA and Interrupt Control Register (Master Mode) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved MSK PR2 –PR0 Bits [15–4]—Reserved. Set to 0. Bit [3]—MSK Mask → Any of the interrupt sources may cause an interrupt if the MSK bit is 0. The interrupt sources cannot cause an interrupt if the MSK bit is 1. The Interrupt Mask Register has a duplicate of this bit. Bits [2–0]—PR [2–0] Priority → These bits define the priority of the serial port interrupts in relation to other interrupt signals. The interrupt priority is the lowest at 7 upon reset. The values of PR2–PR0 are shown above. 5.1.41 DMA1CON/INT6 (036h) and DMA0CON/INT5 (034h) (Slave Mode) DMA and INTerrupt CONtrol Register. The two DMA control registers maintain their original functions and addressing that they possessed in Master Mode. These pins are configured as external interrupts or DMA requests in the respective DMA Control register. The value of these registers is 000Fh at reset (see Table 62). Table 62. DMA and Interrupt Control Register (Slave Mode) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved MSK PR2 –PR0 |
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