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IA186ES Datasheet(PDF) 91 Page - InnovASIC, Inc |
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IA186ES Datasheet(HTML) 91 Page - InnovASIC, Inc |
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91 / 154 page  IA186ES/IA188ES Data Sheet 8-Bit/16-Bit Microcontrollers November 15, 2011 IA211050902-19 http://www.innovasic.com UNCONTROLLED WHEN PRINTED OR COPIED Customer Support: Page 91 of 154 1-888-824-4184 ® Bits [15–0]—PMODE [31–16] PIO Mode 1 Bits → For each bit, if the value is 1, the pin is configured as an input. If 0, an output. The values of these bits correspond to those in the PIO data registers and PIO Mode registers. 5.1.30 T1CON (05eh) and T0CON (056h) Timer0 and Timer1 Mode and CONtrol Registers. These registers control the operation of Timer0 and Timer1, respectively. The value of the T0CON and T1CON registers is 0000h at reset (see Table 51). Table 51. Timer0 and Timer1 Mode and Control Registers 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EN INHn INT RIU 0 0 0 0 0 0 MC RTG P EXT ALT CONT Bit [15]—EN Enable Bit → The timer is enabled when the EN bit is 1. The timer count is inhibited when the EN bit is 0. Setting this bit to 1 by writing to the T2CON register requires that the INHn bit be set to 1 during the same write. This bit is write-only and can only be written if the INHn bit (Bit [14]) is set to 1 in the same operation. Bit [14]—INHn Inhibit Bit → Gates the setting of the enable (EN) bit. This bit must be set to 1 in the same write operation that sets the enable (EN) bit. This bit always reads as 0. Bit [13]—INT Interrupt Bit → An interrupt request is generated when the Count register reaches its maximum, MC = 1, by setting the INT bit to 1. In dual maxcount mode, an interrupt request is generated when the count register reaches the value in maxcount A or maxcount B. No interrupt requests are generated if this bit is set to 0. If an interrupt request is generated and then the enable bit is cleared before said interrupt is serviced, the interrupt request will remain. Bit [12]—RIU Register in Use Bit → This bit is set to 1 when the maxcount register B is used to compare to the timer count value. It is set to 0 when the maxcount compare A register is used. Bits [11–6]—Reserved. Set to 0. Bit [5]—MC Maximum Count → When the timer reaches its maximum count, this bit is set to 1 regardless of the interrupt enable bit. This bit is also set every time maxcount compare register A or B is reached when in dual maxcount mode. This bit may be used by software polling to monitor timer status rather than through interrupts, if desired. Bit [4]—RTG Retrigger Bit. |
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