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IA186ES Datasheet(PDF) 78 Page - InnovASIC, Inc |
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IA186ES Datasheet(HTML) 78 Page - InnovASIC, Inc |
78 / 154 page IA186ES/IA188ES Data Sheet 8-Bit/16-Bit Microcontrollers November 15, 2011 IA211050902-19 http://www.innovasic.com UNCONTROLLED WHEN PRINTED OR COPIED Customer Support: Page 78 of 154 1-888-824-4184 ® The width of the data bus for the lcs_n space should be configured in the AUXCON register before activating the lcs_n chip select pin, by any write access to the LMCS register. The value of the LMCS register is undefined at reset except DA, which is set to 0 (see Table 35). Table 35. Low-Memory Chip Select Register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 UB2 –UB0 1 1 1 1 DA PSE 1 1 1 R2 R1-R0 Bit [15]—Reserved. Set to 0. Bits [14–12]—UB [2–0] → Upper Boundary. These bits define the upper boundary of memory accessed by the lcs_n chip select. The LMCS Block-Size Programming Values shown below list the possible block-size configurations (a 512-Kbyte maximum). LMCS Block-Size Programming Values Memory Block Size Ending Address UB2 –UB0 64K 0FFFFh 000b 128K 1FFFFh 001b 256K 3FFFFh 011b 512K 7FFFFh 111b Bits [11–8]—Reserved. Set to 1. Bit [7]—DA Disable Address → When set to 1, the address bus is disabled, providing some measure of power saving. When 0, the address is driven onto the address bus ad15–ad0 during the address phase of a bus cycle. This bit is set to 0 at reset. – If bhe_n/aden_n is held at 0 during the rising edge of res_n, the address bus is always driven, regardless of the setting of DA. Bit [6]—PSE PSRAM Mode Enable → When set to 1, PSRAM support for the lcs_n chip select memory space is enabled. The EDRAM, MDRAM, and CDRAM RCU registers must be configured for auto refresh before PSRAM support is enabled. Setting the enable bit (EN) in the enable RCU register (EDRAM, offset e4h) configures the mcs3_n/rfsh_n as rfsh_n. Bits [5–3]—Reserved. Set to 1. Bit [2]—R2 Ready Mode → When set to 1, the external ready is ignored. When 0, it is required. The value of these bits determines the number of wait states inserted. |
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