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IA186ES Datasheet(PDF) 74 Page - InnovASIC, Inc |
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IA186ES Datasheet(HTML) 74 Page - InnovASIC, Inc |
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74 / 154 page  IA186ES/IA188ES Data Sheet 8-Bit/16-Bit Microcontrollers November 15, 2011 IA211050902-19 http://www.innovasic.com UNCONTROLLED WHEN PRINTED OR COPIED Customer Support: Page 74 of 154 1-888-824-4184 ® Table 32. MCS and PCS Auxiliary Register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 M6 –M0 EX MS 1 1 1 R2 R1 –R0 Bit [15]—Reserved → Set to 1. Bits [14–8]—M [6–0] mcs_n Block Size → These seven bits determine the total memory block size for the mcs3_n–mcs0_n chip selects. The size is divided equally among them. The relationship between M [6–0] and the size is shown below. Select Sizes of M6 –M0 by Total Block Size Total Block Size Individual Select Size M6 –M0 8K 2K 0000001b 16K 4K 0000010b 32K 8K 0000100b 64K 16K 0001000b 128K 32K 0010000b 256K 64K 0100000b 512K 128K 1000000b Bit [7]—EX Pin Selector → This bit determines whether the pcs6_n–pcs5_n pins are configured as chip selects or as alternate outputs for a2 and a1. When set to 1, they are configured as peripheral chip select pins. When 0, they become address bits a1 and a2, respectively. Bit [6]—MS → Memory/ I/O Space Selector determines whether the pcs_n pins are active during either memory or I/O bus cycles. When set to 1, the outputs are active for memory bus cycles. When 0, they are active for I/O bus cycles. Bits [5–3]—Reserved → Set to 1. Bit [2]—R2 Ready Mode → This bit influences only the pcs6_n–pcs5_n chip selects. When set to 1, external ready is ignored. When 0, it is required. Values determine the number of wait states to be inserted. Bits [1–0]—R [1–0] Wait-State Value → These bits influence only the pcs6_n–pcs5_n chip selects. Their value determines the number of wait states inserted into an access, depending on whether it is to the pcs_n memory or I/O area. Up to three wait states can be inserted (R1–R0 = 00b to 11b). |
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