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IA186ES Datasheet(PDF) 62 Page - InnovASIC, Inc |
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IA186ES Datasheet(HTML) 62 Page - InnovASIC, Inc |
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62 / 154 page  IA186ES/IA188ES Data Sheet 8-Bit/16-Bit Microcontrollers November 15, 2011 IA211050902-19 http://www.innovasic.com UNCONTROLLED WHEN PRINTED OR COPIED Customer Support: Page 62 of 154 1-888-824-4184 ® These default status settings may be changed as desired. After POR, a19–a17, the three most significant bits of the address bus, start with their normal function, allowing the processor to begin fetching instructions from the boot address FFFF0h. Normal function is also the default setting for dt/r_n, den_n, and srdy after POR. If the ad15–ad0 bus override is enabled, s6/clkdiv2_n and uzi_n automatically return to normal operation. The ad15–ad0 bus override is enabled if either the bhe_n/aden_n for the IA186ES or the rfsh2_n/aden_n for the IA188ES is held low during POR. 5. Peripheral Architecture 5.1 Control and Registers The on-chip peripherals in the IA186ES/IA188ES are controlled from a 256-byte block of internal registers. Although these registers are actually located in the peripherals they control, they are addressed within a single 256-byte block of I/O space and are treated as a functional unit. A list of these registers is presented in Table 16. Although a named register may be 8 bits, write operations performed on the IA188ES should be 8-bit writes, resulting in 16-bit data transfers to the Peripheral Control Block (PCB) register. Only word reads should be performed to the PCB registers. If unaligned read and write accesses are performed on either the IA186ES or IA188ES, indeterminate behavior may result. Note: Adhere to these directions while writing code to avoid errors. |
Similar Part No. - IA186ES_11 |
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