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IA186ES Datasheet(PDF) 6 Page - InnovASIC, Inc |
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IA186ES Datasheet(HTML) 6 Page - InnovASIC, Inc |
6 / 154 page ![]() IA186ES/IA188ES Data Sheet 8-Bit/16-Bit Microcontrollers November 15, 2011 IA211050902-19 http://www.innovasic.com UNCONTROLLED WHEN PRINTED OR COPIED Customer Support: Page 6 of 154 1-888-824-4184 ® 4.13 Midrange-Memory Chip Selects .................................................................................52 4.14 Peripheral Chip Selects ...............................................................................................53 4.15 Refresh Control ...........................................................................................................53 4.16 Interrupt Control..........................................................................................................53 4.17 Interrupt Types ............................................................................................................54 4.18 Timer Control ..............................................................................................................55 4.19 Watchdog Timer..........................................................................................................56 4.20 Direct Memory Access................................................................................................57 4.21 DMA Operation...........................................................................................................57 4.22 DMA Channel Control Registers ................................................................................58 4.23 DMA Priority ..............................................................................................................59 4.24 Pulse Width Demodulation .........................................................................................59 4.25 Asynchronous Serial Ports ..........................................................................................60 4.26 Programmable I/O .......................................................................................................60 5. Peripheral Architecture .........................................................................................................62 5.1 Control and Registers ..................................................................................................62 5.1.1 RELREG (0feh) ..............................................................................................64 5.1.2 RESCON (0f6h)..............................................................................................64 5.1.3 PRL (0f4h) ......................................................................................................64 5.1.4 AUXCON (0f2h) ............................................................................................65 5.1.5 SYSCON (0f0h)..............................................................................................66 5.1.6 WDTCON (0e6h) ...........................................................................................67 5.1.7 EDRAM (0e4h) ..............................................................................................68 5.1.8 CDRAM (0e2h) ..............................................................................................69 5.1.9 MDRAM (0e0h) .............................................................................................69 5.1.10 D1CON (0dah) and D0CON (0cah) ...............................................................69 5.1.11 D1TC (0d8h) and D0TC (0c8h) .....................................................................71 5.1.12 D1DSTH (0d6h) and D0DSTH (0c6h)...........................................................72 5.1.13 DIDSTL (0d4h) and D0DSTL (0c4h) ............................................................72 5.1.14 D1SRCH (0d2h) and D0SRCH (0c2h)...........................................................72 5.1.15 D1SRCL (0d0h) and D0SRCL (0c0h)............................................................73 5.1.16 MPCS (0a8h) ..................................................................................................73 5.1.17 MMCS (0a6h) .................................................................................................75 5.1.18 PACS (0a4h) ...................................................................................................76 5.1.19 LMCS (0a2h) ..................................................................................................77 5.1.20 UMCS (0a0h)..................................................................................................79 5.1.21 SP0BAUD (088h) ...........................................................................................80 5.1.22 SP1BAUD (018h) ...........................................................................................80 5.1.23 SP0RD (086h) and SP1RD (016h) .................................................................81 5.1.24 SP0TD (084h) and SP1TD (014h)..................................................................82 5.1.25 SP0STS (082h) and SP1STS (012h)...............................................................82 5.1.26 SP0CT (080h) and SP1CT (010h) ..................................................................84 |
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