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IA186ES Datasheet(PDF) 59 Page - InnovASIC, Inc |
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IA186ES Datasheet(HTML) 59 Page - InnovASIC, Inc |
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59 / 154 page  IA186ES/IA188ES Data Sheet 8-Bit/16-Bit Microcontrollers November 15, 2011 IA211050902-19 http://www.innovasic.com UNCONTROLLED WHEN PRINTED OR COPIED Customer Support: Page 59 of 154 1-888-824-4184 ® Whether DMA transfers cease upon reaching a designated count (Bit [9]) Whether the last transfer generates an interrupt (Bit [8]) Synchronization mode (Bits [7–6]) The relative priority of one DMA channel with respect to the other (Bit [5]) Acceptance of DMA requests from Timer2 (Bit [4]) Configuration of DRQ pins as INT (Bit [3]) Byte or Word transfers (Bit [0]) 4.23 DMA Priority With the exception of word accesses to odd memory locations or between locked memory addresses, DMA transfers have a higher priority than CPU transfers. Because the CPU cannot access memory during a DMA transfer and a DMA transfer cannot be suspended by an interrupt request, continuous DMA activity will increase interrupt delay. An NMI request halts any DMA activity, however, enabling the CPU to respond promptly to the request. 4.24 Pulse Width Demodulation Note: There is no support for analog-to-digital conversion. This feature provides a means of measuring the width of a pulse in both its high and low phases. Its enabled by the PWD bit (Bit [6]) in the SYSCON. TMRIN0, TMRIN1, INT2, and INT4 are internally configured to support the detection of rising and falling edges on the PWD pin (int2/int0_n/pwd) and to enable either timer0 or timer1, depending on whether the signal is high or low (see Figure 11). Because they are not used in this mode, the tmrin0, tmrin1, and int4 pins are available as PIO pins. Figure 11. Typical Waveform at the int2/int0_n/pwd pin int2 int4 int2 Interrupts generated timer1 enabled timer0 enabled |
Similar Part No. - IA186ES_11 |
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Similar Description - IA186ES_11 |
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