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ADA4666-2 Datasheet(PDF) 19 Page - Analog Devices |
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ADA4666-2 Datasheet(HTML) 19 Page - Analog Devices |
19 / 32 page Data Sheet ADA4666-2 Rev. 0 | Page 19 of 32 Figure 54. Positive Settling Time to 0.1% Figure 55. Negative Settling Time to 0.1% Figure 56. Voltage Noise Density vs. Frequency Figure 57. Positive Settling Time to 0.1% Figure 58. Negative Settling Time to 0.1% Figure 59. Voltage Noise Density vs. Frequency TIME (400ns/DIV) VSY = ±1.5V VIN = 1V p-p RL = 10kΩ CL = 10pF AV = –1 ERROR BAND OUTPUT INPUT TIME (400ns/DIV) VSY = ±1.5V VIN = 1V p-p RL = 10kΩ CL = 10pF AV = –1 ERROR BAND OUTPUT INPUT 1 10 100 1k 1k 10k 100k 10 100 1M 10M FREQUENCY (Hz) VSY = 3V VCM = VSY/2 AV = 1 TIME (400ns/DIV) VSY = ±9V VIN = 1V p-p RL = 10kΩ CL = 10pF AV = –1 ERROR BAND OUTPUT INPUT TIME (400ns/DIV) VSY = ±9V VIN = 1V p-p RL = 10kΩ CL = 10pF AV = –1 ERROR BAND OUTPUT INPUT 1 10 100 1k 1k 10k 100k 10 100 1M 10M FREQUENCY (Hz) VSY = 18V VCM = VSY/2 AV = 1 |
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