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S1C17564 Datasheet(PDF) 3 Page - Epson Company |
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S1C17564 Datasheet(HTML) 3 Page - Epson Company |
3 / 4 page S1C17554/564 BLOCK DIAGRAM S1C17554 CPU Core S1C17 Internal RAM (16K bytes) Flash memory (128K bytes) Test circuit Reset circuit Interrupt controller 16-bit timer (3ch.) Fine m ode 16-bit timer (2ch.) UART (2ch.) SPI (3ch.) I2C master I 2C slave A/D converter MISC register Clock register (with oscillators) Clock timer Stopwatch timer Watchdog timer 16-bit PWM tim er (4ch.) IR remote controller I/O 2 (0x5000-) I/O 1 (0x4000-) TEST #RESET SINx, SOUTx, SCLKx SDIx, SDOx, SPICLKx, #SPISSx SDA0, SCL0 SDA1, SCL1, #BFR Pxx REMI, REMO EXCLx, CAPx, TOUTx OSC1-2, OSC3-4, FOUTA, FOUTB AVDD AINx, #ADTRG DCLK, DST2, DSIO 32 bits 16 bits 8/16 bits 8/16 bits I/O prt/ Port MUX CPU Core S1C17 Internal RAM (16K bytes) Flash memory (128K bytes) Test circuit Reset circuit Interrupt controller 16-bit timer (3ch.) Fine m ode 16-bit timer (2ch.) UART (2ch.) SPI (3ch.) I2C master I 2C slave A/D converter MISC register Clock register (with oscillators) Clock timer Stopwatch timer Watchdog timer 16-bit PWM tim er (4ch.) IR remote controller I/O 2 (0x5000-) I/O 1 (0x4000-) TEST #RESET SINx, SOUTx, SCLKx SDIx, SDOx, SPICLKx, #SPISSx SDA0, SCL0 SDA1, SCL1, #BFR Pxx REMI, REMO EXCLx, CAPx, TOUTx OSC1-2, OSC3-4, FOUTA, FOUTB AVDD AINx, #ADTRG DCLK, DST2, DSIO 32 bits 16 bits 8/16 bits 8/16 bits I/O prt/ Port MUX 3 |
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