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S1C17555 Datasheet(PDF) 4 Page - Epson Company |
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S1C17555 Datasheet(HTML) 4 Page - Epson Company |
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4 / 5 page  S1C17555/565/955/965 4 Seiko Epson Corporation CPU Core S1C17 Internal RAM1 (4K bytes) Flash memory (128K bytes) Reset circuit Interrupt controller 16-bit timer (3 ch.) Fine mode 16-bit timer (2 ch.) UART (1 ch.) 8-bit SPI (2 ch.) 16-bit SPI (1 ch.) I2C master (1 ch.) I2C slave (1 ch.) FSA Internal RAM2 (FSA RAM) (12K bytes) MISC register Clock generator (with oscillators) Clock timer Stopwatch timer W atchdog timer 16-bit PWM timer (4 ch.) I/O port/ port MUX DCLK, DST2, DSIO OSC1-2 FOUTA, FOUTB EXCL0-2, MSCLK CAPA0-2, TOUTA0-2 P00-07, P10-17, P20-23 LVDD, HVDD VPP #RESET SIN0, SOUT0, SCLK0 SDI0-1, SDO0-1, SPICLK0-1, #SPISS0-1 SDI2, SDO2, SPICLK2, SPISS2 SDAM, SCLM SDAS, SCLS #BFR 32 bits 16 bits 32 bits 32 bits 8/16 bits 8/16 bits CPU Core S1C17 Internal RAM1 (4K bytes) Flash memory (128K bytes) Reset circuit Interrupt controller 16-bit timer (3 ch.) Fine mode 16-bit timer (2 ch.) UART (1 ch.) 8-bit SPI (2 ch.) 16-bit SPI (1 ch.) I2C master (1 ch.) I2C slave (1 ch.) FSA Internal RAM2 (FSA RAM) (12K bytes) MISC register Clock generator (with oscillators) Clock timer Stopwatch timer W atchdog timer 16-bit PWM timer (4 ch.) I/O port/ port MUX DCLK, DST2, DSIO OSC1-2 FOUTA, FOUTB EXCL0-2, MSCLK CAPA0-2, TOUTA0-2 P00-07, P10-17, P20-23 LVDD, HVDD VPP #RESET SIN0, SOUT0, SCLK0 SDI0-1, SDO0-1, SPICLK0-1, #SPISS0-1 SDI2, SDO2, SPICLK2, SPISS2 SDAM, SCLM SDAS, SCLS #BFR 32 bits 16 bits 32 bits 32 bits 8/16 bits 8/16 bits S1C17955 S1C17965 CPU Core S1C17 Internal RAM (4K bytes) Flash memory (128K bytes) Reset circuit Interrupt controller 16-bit timer (3 ch.) Fine mode 16-bit timer (2 ch.) UART (2 ch.) 8-bit SPI (2 ch.) 16-bit SPI (1 ch.) I2C master (1 ch.) I2C slave (1 ch.) FSA Internal RAM2 (FSA RAM) (12K bytes) Regulator 12-bit A/D converter MISC register Clock generator (with oscillators) Clock timer Stopwatch timer Watchdog timer 16-bit PWM timer (4 ch.) IR remote controller I/O port/ port MUX DCLK, DST2, DSIO VINL, VINA, VINP, REGEN C1P, C1N, C1H, C2P, C2N AVDD, AVSS AINx ITRS OSC1-2, OSC3-4 FOUTA, FOUTB EXCL0-2, MSCLK CA`A0-3, TOUTA0-3 REMI, REMO P00-07, P10-17, P20-27 LVDD, HVDD VPP #RESET SIN0-1, SOUT0-1, SCLK0-1 SDI0-1, SDO0-1, SPICLK0-1, #SPISS0-1 SDI2, SDO2, SPICLK2, SPISS2 SDAM, SCLM SDAS, SCLS #BFR 32 bits 16 bits 32 bits 32 bits 8/16 bits 8/16 bits CPU Core S1C17 Internal RAM (4K bytes) Flash memory (128K bytes) Reset circuit Interrupt controller 16-bit timer (3 ch.) Fine mode 16-bit timer (2 ch.) UART (2 ch.) 8-bit SPI (2 ch.) 16-bit SPI (1 ch.) I2C master (1 ch.) I2C slave (1 ch.) FSA Internal RAM2 (FSA RAM) (12K bytes) Regulator 12-bit A/D converter MISC register Clock generator (with oscillators) Clock timer Stopwatch timer Watchdog timer 16-bit PWM timer (4 ch.) IR remote controller I/O port/ port MUX DCLK, DST2, DSIO VINL, VINA, VINP, REGEN C1P, C1N, C1H, C2P, C2N AVDD, AVSS AINx ITRS OSC1-2, OSC3-4 FOUTA, FOUTB EXCL0-2, MSCLK CA`A0-3, TOUTA0-3 REMI, REMO P00-07, P10-17, P20-27 LVDD, HVDD VPP #RESET SIN0-1, SOUT0-1, SCLK0-1 SDI0-1, SDO0-1, SPICLK0-1, #SPISS0-1 SDI2, SDO2, SPICLK2, SPISS2 SDAM, SCLM SDAS, SCLS #BFR 32 bits 16 bits 32 bits 32 bits 8/16 bits 8/16 bits |
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