S1C17F13

16-bit Single Chip Microcontroller for Active EPD

■ DESCRIPTIONS

The S1C17F13 is an ultra low-power MCU equipped with a display memory and an EPD timing controller to

send display data for using the active EPD panels. This IC includes the synchronous serial interface, parallel

interface, UART, and I2C to communicate with an EPD panel and other devices. This IC allows measurement of

various environmental conditions such as a temperature and humidity measurement using the R/F converter,

and a supply voltage measurement using the supply voltage detector and brownout reset circuits.

FEATURES

CPU

CPU core

Seiko Epson original 16-bit RISC CPU core S1C17

16-bit × 16-bit multiplier

16-bit × 16-bit + 32-bit multiply and accumulation unit

Multiplier/Divider (COPRO)

16-bit ÷ 16-bit divider

Other

On-chip debugger

Embedded Flash memory

Capacity

128K bytes (for both instructions and data) *1

Erase/program count

50 times (min.) * Programming by the debugging tool ICDmini

Security function to protect from reading/programming by ICDmini

On-board programming function using ICDmini

Other

Embedded Flash voltage booster to generate the Flash erasing/programming voltage

Embedded RAM

6K bytes (area accessed by CPU only)

Capacity

14K bytes (area accessed by CPU and EPD Tcon)

Clock generator (CLG)

System clock source

5 sources (OSC3B, OSC3A, OSC1B, OSC1A, and EXOSC)

System clock frequency (operating

frequency)

20 MHz (max.)

OSC3B internal high-speed oscillator circuit

(boot clock source)

20/16/12/8 MHz (typ.) selectable via software

OSC1B internal low-speed oscillator circuit

32 kHz (typ.)

OSC3A high-speed oscillator circuit

20 MHz (max.) crystal or ceramic oscillator circuit

OSC1A low-speed oscillator circuit

32.768 kHz (typ.) crystal oscillator circuit

EXOSC clock input

20 MHz (max.) square or sine wave input

Configurable system clock division ratio

Configurable system clock (except for OSC1A and OSC1B) used at wake up from SLEEP

state

Other

Operating clock frequency for the CPU and all peripheral circuits is selectable.

I/O port (PPORT)

Number of general-purpose I/O ports

37 bits (max.) (Pins are shared with the peripheral I/O.)

Number of input interrupt ports

8 bits

All pins contain a pull-up/down resistor that can be enabled/disabled via software

Other

16 bits contain an interrupt function and a chattering filter function.

Display control

Controls display on the active-matrix EPD via the embedded SPI or PIO.

Includes a display data read function from the embedded RAM (area for both CPU and

EPD Tcon).

EPD timing controller (EPD Tcon)

Can be controlled with the dedicated API library.

Communication interfaces

1 channel

IrDA1.0 supported

UART (UART)

Embedded baud-rate generator

3 channels

Synchronous serial interface (SPI)

Configurable as the communication interface for EPD Tcon (SPI Ch.1)

1 channel

Master and slave operations supported

I

Embedded baud-rate generator

Address length: 8 bits (max.)

Data width: 8 bits (max.)

Parallel interface (PIO)

Control signals: #CE, #RD, #WR