AD5662ARJ-1REEL7 datasheet(16/24 Pages) AD

Part #	AD5662ARJ-1REEL7

Description	16-Bit nanoDAC in a SOT-23

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Manufacturer	AD [Analog Devices]

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AD5662

Rev. A | Page 16 of 24

POWER-DOWN MODES

The AD5662 contains four separate modes of operation. These

modes are software-programmable by setting two bits (DB17

and DB16) in the control register. Table 5 shows how the state

of the bits corresponds to the device’s mode of operation.

Table 5. Modes of Operation for the AD5662

DB17

DB16

Operating Mode

0

Normal Operation

Power-Down Modes

0

1

1 kΩ to GND

1

0

100 kΩ to GND

1

Three-State

When both bits are set to 0, the part works normally with its

normal power consumption of 250 μA at 5 V. However, for the

three power-down modes, the supply current falls to 480 nA at

5 V (100 nA at 3 V). Not only does the supply current fall, but

the output stage is also internally switched from the output of

the amplifier to a resistor network of known values. This has the

advantage that the output impedance of the part is known while

the part is in power-down mode. The outputs can either be

connected internally to GND through a 1 kΩ or 100 kΩ

resistor, or left open-circuited (three-state) (see Figure 36).

RESISTOR

NETWORK

VOUT

RESISTOR

STRING DAC

POWER-DOWN

CIRCUITRY

AMPLIFIER

Figure 36. Output Stage During Power-Down

The bias generator, the output amplifier, the resistor string, and

other associated linear circuitry are shut down when power-

down mode is activated. However, the contents of the DAC

register are unaffected when in power-down. The time to exit

power-down is typically 4 μs for VDD = 5 V and for VDD = 3 V

(see Figure 24).

MICROPROCESSOR INTERFACING

AD5662 to Blackfin® ADSP-BF53x Interface

Figure 37 shows a serial interface between the AD5662 and

the Blackfin ADSP-BF53x microprocessor. The ADSP-BF53x

processor family incorporates two dual-channel synchronous

serial ports, SPORT1 and SPORT0, for serial and multiprocessor

communications. Using SPORT0 to connect to the AD5662, the

setup for the interface is as follows. DT0PRI drives the DIN pin

of the AD5662, while TSCLK0 drives the SCLK of the part. The

SYNC is driven from TFS0.

AD5662*

*ADDITIONAL PINS OMITTED FOR CLARITY

TFS0

DTOPRI

TSCLK0

SYNC

DIN

SCLK

ADSP-BF53x*

Figure 37. AD5662 to Blackfin ADSP-BF53x Interface

AD5662 to 68HC11/68L11 Interface

Figure 38 shows a serial interface between the AD5662 and the

68HC11/68L11 microcontroller. SCK of the 68HC11/68L11

drives the SCLK of the AD5662, while the MOSI output drives

the serial data line of the DAC.

The SYNC signal is derived from a port line (PC7). The setup

conditions for correct operation of this interface are as follows.

The 68HC11/68L11 is configured with its CPOL bit as a 0 and

its CPHA bit as a 1. When data is being transmitted to the DAC,

the SYNC line is taken low (PC7). When the 68HC11/ 68L11 is

configured as described above, data appearing on the MOSI

output is valid on the falling edge of SCK. Serial data from the

68HC11/68L11 is transmitted in 8-bit bytes with only eight

falling clock edges occurring in the transmit cycle. Data is

transmitted MSB first. In order to load data to the AD5662, PC7

is left low after the first eight bits are transferred, and a second

serial write operation is performed to the DAC; PC7 is taken

high at the end of this procedure.

AD5662*

*ADDITIONAL PINS OMITTED FOR CLARITY

PC7

SCK

MOSI

SYNC

SCLK

DIN

68HC11/68L11*

Figure 38. AD5662 to 68HC11/68L11 Interface

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