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511BBA200M000BAG Datasheet(PDF) 12 Page - Silicon Laboratories |
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511BBA200M000BAG Datasheet(HTML) 12 Page - Silicon Laboratories |
12 / 26 page ![]() Si510/511 12 Rev. 1.1 2. Pin Descriptions *Supports integrated 1:2 CMOS buffer. See ordering information and section 2.1“Dual CMOS Buffer”. Table 11. Si510 Pin Descriptions (CMOS) Pin Name CMOS Function 1 OE Output Enable. Includes internal pull-up for OE active high. Includes internal pull-down for OE active low. See ordering information. 2 GND Electrical and Case Ground. 3 CLK Clock Output. 4 VDD Power Supply Voltage. Table 12. Si510 Pin Descriptions (LVPECL/LVDS/HCSL, Dual CMOS, OE Pin 2) Pin Name LVPECL/LVDS/HCSL Function 1 NC No connect. Make no external connection to this pin. 2 OE Output Enable. Includes internal pull-up for OE active high. Includes internal pull-down for OE active low. See ordering information. 3 GND Electrical and Case Ground. 4 CLK+ Clock Output. 5 CLK– Complementary Clock Output. 6 VDD Power Supply Voltage. Table 13. Si511 Pin Descriptions (LVPECL/LVDS/HCSL, Dual CMOS, OE Pin 1) Pin Name LVPECL/LVDS/HCSL Function 1 OE Output Enable. Includes internal pull-up for OE active high. Includes internal pull-down for OE active low. See ordering information. 2 NC No connect. Make no external connection to this pin. 3 GND Electrical and Case Ground. 4 CLK+ Clock Output. 5 CLK– Complementary Clock Output. 6 VDD Power Supply Voltage. 1 2 3 6 5 4 GND OE VDD CLK+ CLK–* NC 1 2 3 6 5 4 GND NC VDD CLK+ CLK–* OE Si510 (CMOS) Si510 (LVDS/LVPECL/HCSL/Dual CMOS*) Si511 (LVDS/LVPECL/HCSL/DualCMOS)*) 1 2 4 3 GND VDD CLK OE |
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