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Rev. 0.09a : 2011.09.14

R1QGA36**CB* / R1QKA36**CB* Series

JTAG Specification

These products support a limited set of JTAG functions as in IEEE standard 1149.1.

Disabling the Test Access Port

It is possible to use this device without utilizing the TAP. To disable the TAP controller without interfering with

normal operation of the device, TCK must be tied to V

TDI and TMS are internally pulled up and may be unconnected, or may be connected to VDD through a pull up

resistor.

TDO should be left unconnected.

1R

11R

10R

2R

Pin assignments

Test mode select. This is the command input for the TAP

controller state machine.

TMS

Test data input. This is the input side of the serial registers

placed between TDI and TDO. The register placed between

TDI and TDO is determined by the state of the TAP controller

state machine and the instruction that is currently loaded in

the TAP instruction.

TDI

Test data output. Output changes in response to the falling

edge of TCK. This is the output side of the serial registers

placed between TDI and TDO.

TDO

Test Access Port (TAP) Pins

Notes:

The device does not have TRST (TAP reset). The Test-Logic Reset state is entered while

TMS is held high for five rising edges of TCK. The TAP controller state is also reset on SRAM

POWER-UP.

Notes

Test clock input. All inputs are captured on the rising edge of

TCK and all outputs propagate from the falling edge of TCK.

TCK

Description

Symbol I/O

Common

R10DS0161EJ0009