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R1QKA3618CBG Datasheet(PDF) 25 Page - Renesas Technology Corp

Part # R1QKA3618CBG
Description  36-Mbit QDRII SRAM 4-word Burst
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

R1QKA3618CBG Datasheet(HTML) 25 Page - Renesas Technology Corp

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PAGE : 25
Rev. 0.09a : 2011.09.14
R1QGA36**CB* / R1QKA36**CB* Series
hinS=00000.0000.0000.0100.0100---
00000.0000.0000.0100.0100
---00000.0000.0000.0100.0100---
R1QA_RL=2.0
R
tQVLD
-tQVLD
tQVLD
-tQVLD
Q00
Qx3
Q01 Q02 Q03 Q20 Q21 Q22 Q23
Qx2
Qx1
tCHQV
-tCHQX
tCHQV
-tCHQX
tCQHQV
-tCQHQX
-tCHQX1
tCHQZ
tCHCQV
-tCHCQX
tCHCQV
-tCHCQX
Timing Waveforms
Read and Write Timing (QDRII+, B4, Read Latency = 2.0 cycle)
K
A0
D10
A1
A2
A3
D11 D12 D13 D30 D31 D32 D33
NOP
READ
WRITE
READ
WRITE
NOP
NOP
NOP
tKHIX
tIVKH
tKHIX
tIVKH
tKHAX
tAVKH
tKHDX
tDVKH
tKHDX
tDVKH
/K
/R
/W
Address
Data in
tKHKH
tKHKL
tKLKH
tKH/KH
t/KHKH
Data out
CQ
/CQ
Notes:
1.
Q00 refers to output from address A0+0. Q01 refers to output from the next internal burst address
following A0, i.e., A0+1.
2.
Outputs are disabled (high-Z) N clock cycle after the last read cycle. Here, N = Read Latency + Burst
Length
0.5.
3.
In this example, if address A2 = A1, then data Q20 = D10, Q21 = D11. Write data is forwarded
immediately as read results.
4.
To control read and write operations, /BW signals must operate at the same timing as Data-in signals.
1
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QVLD
R10DS0161EJ0009


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