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R1QKA3618CBG Datasheet(PDF) 23 Page - Renesas Technology Corp |
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R1QKA3618CBG Datasheet(HTML) 23 Page - Renesas Technology Corp |
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23 / 38 page  PAGE : 23 Rev. 0.09a : 2011.09.14 R1QGA36**CB* / R1QKA36**CB* Series hinS=00000.0000.0000.0111.0111--- 00000.0000.0000.0111.0111- -- 00000.0000.0000.0000.0000---RL=2.0 /CQ high to QVLD valid K, /K high to output low-Z K, /K high to output high-Z CQ, /CQ high to output hold CQ, /CQ high to output valid K, /K high to echo clock hold K, /K high to echo clock valid K, /K high to output hold K, /K high to output valid Output Times K static to DLL/PLL reset Lock time (K) Clock phase jitter (K, /K) DLL/PLL Timing /Clock to clock (/K to K) Clock to /clock (K to /K) Clock low time (K, /K) Clock high time (K, /K) Average clock cycle time (K, /K) Clock Parameter AC Characteristics (Read Latency = 2.0 cycle) (Ta = 0 ~ +70 C @ R1Q*A*****BG-**R** series) (Ta = -40 ~ +85 C @ R1Q*A*****BG-**I** series) (V DD =1.8V 0.1V, V DDQ = 1.5V, VREF = 0.75V) t QVLD t CHQX1 t CHQZ t CQHQX t CQHQV t CHCQX t CHCQV t CHQX t CHQV t KC reset t KC lock t KC var t /KHKH t KH/KH t KLKH t KHKL t KHKH Symbol 0.15 0.35 0.15 0.35 0.35 30 20 0.425 0.425 0.40 0.40 1.875 Min -19 0.15 0.55 0.15 0.55 0.55 0.15 4.00 Max 0.15 0.35 0.15 0.35 0.35 30 20 0.425 0.425 0.40 0.40 2.00 Min -20 0.15 0.55 0.15 0.55 0.55 0.15 4.00 Max 0.15 0.35 0.15 0.35 0.35 30 20 0.425 0.425 0.40 0.40 2.22 Min -22 0.15 0.55 0.15 0.55 0.55 0.15 4.00 Max 0.20 0.35 0.20 0.35 0.35 30 20 0.425 0.425 0.40 0.40 2.50 Min -25 0.20 0.55 0.20 0.55 0.55 0.20 4.00 Max 0.20 0.35 0.20 0.35 0.35 30 20 0.425 0.425 0.40 0.40 2.66 Min -27 0.20 0.55 0.20 0.55 0.55 0.20 4.00 Max 0.20 0.35 0.20 0.35 0.35 30 20 0.425 0.425 0.40 0.40 3.00 Min -30 0.20 0.55 0.20 0.55 0.55 0.20 4.00 Max ns ns ns ns ns ns ns ns ns ns us ns Cy- cle Cy- cle Cy- cle Cy- cle ns Unit 7 5 5, 6 4, 7 4, 7 7 2 3 Notes R10DS0161EJ0009 |
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