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R1QKA3618CBG Datasheet(PDF) 20 Page - Renesas Technology Corp |
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R1QKA3618CBG Datasheet(HTML) 20 Page - Renesas Technology Corp |
20 / 38 page ![]() PAGE : 20 Rev. 0.09a : 2011.09.14 R1QGA36**CB* / R1QKA36**CB* Series Common Leakage Currents & Output Voltage 8, 9 |I OH| 0.1 mA V V DDQ V DDQ 0.2 V OH (Low) Output high voltage 8, 9 Note 6 V V DDQ/2 0.12 V DDQ/2 0.12 V OH V DDQ/2 0.12 0.2 5 2 Max V V A A Unit Notes: 1. All inputs (except ZQ, V REF) are held at either VIH or VIL. 2. I OUT = 0 mA. VDD = VDD max, tKHKH = tKHKH min. 3. Operating supply currents (I DD) are measured at 100% bus utilization. IDD of QDR family is current of device with 100% write and 100% read cycle. I DD of DDR family is current of device with 100% write cycle (if I DD(Write) > IDD(Read)) or 100% read cycle (if IDD(Write) < IDD(Read)). 4. All address / data inputs are static at either V IN > VIH or VIN < VIL. 5. Reference value. (Condition = NOP currents are valid when entering NOP after all pending READ and WRITE cycles are completed. ) 6. Outputs are impedance-controlled. |I OH| = (VDDQ/2)/(RQ/5) for values of 175 RQ 350 . 7. Outputs are impedance-controlled. I OL = (VDDQ/2)/(RQ/5) for values of 175 RQ 350 . 8. AC load current is higher than the shown DC values. AC I/O curves are available upon request. 9. HSTL outputs meet JEDEC HSTL Class I and Class II standards. 10. 0 V IN V DDQ for all input balls (except VREF, ZQ, TCK, TMS, TDI ball). If R1QD, R1QE, R1QF, R1QK, R1QL, R1QM, R1QP series, balls with ODT do not follow this spec. 11. 0 V OUT V DDQ (except TDO ball), output disabled. Note 7 I OL 0.1 mA Test condition 11 5 I LO Output leakage current 8, 9 V SS V OL (Low) Output low voltage 8, 9 V DDQ/2 0.12 V OL 10 2 I LI Input leakage current Notes Min Symbol Parameter R10DS0161EJ0009 |
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